J
Josh Pfrimmer
Guest
Hi experts,
I've looked through the archives, and the Xilinx literature, and haven't
found an answer to this question, so please forgive me if it's obvious
and/or everyone's sick of answering. I've spent a couple of days on this.
I'm upgrading a lab here at UVic from an xc4000 based board to a Spartan2.
So as not to complicate the upgrade needlessly, we'd like to stick with
Foundation 4.2i tools and design flow. (We'll upgrade that next semester..
one thing at a time.) The students are to create a pipelined 8-bit
processor in either VHDL or Schematic. They use the Foundation simulator
to debug.
The first issue I came up against was that they now have to use CoreGen to
make memories (program, data, stack), where we used to use LogicBlox.
Specifying memory contents in LogicBlox used a .mem file. In Coregen, you
have to use a .coe file. Easy enough, and when I go all the way through
implementation, I have no problems at all.
When I want to do a functional simulation, however, the program memory is
all zeroes. How best to go about getting the .coe data into the Foundation
functional simulator? The VHDL and verilog files reference a .mif file.
The simulator allows one to "load contents" via a hex file.
I'd prefer a solution that only requires students to edit one file to
change the program for both the hardware implementation (I've noticed that
CoreGen puts the correct data in the EDIF file) AND the simulation. It's a
pretty challenging lab as it is, without the extra pitfall of having
mismatching simulation/hardware programs.
Thanks for your time,
JP
--
Josh Pfrimmer, B.Eng.
_________________________________________
University of Victoria, ECE
jpfrimmer<AT>ece<DOT>uvic<DOT>ca
_________________________________________
->My views and opinions are not necessarily UVic's
I've looked through the archives, and the Xilinx literature, and haven't
found an answer to this question, so please forgive me if it's obvious
and/or everyone's sick of answering. I've spent a couple of days on this.
I'm upgrading a lab here at UVic from an xc4000 based board to a Spartan2.
So as not to complicate the upgrade needlessly, we'd like to stick with
Foundation 4.2i tools and design flow. (We'll upgrade that next semester..
one thing at a time.) The students are to create a pipelined 8-bit
processor in either VHDL or Schematic. They use the Foundation simulator
to debug.
The first issue I came up against was that they now have to use CoreGen to
make memories (program, data, stack), where we used to use LogicBlox.
Specifying memory contents in LogicBlox used a .mem file. In Coregen, you
have to use a .coe file. Easy enough, and when I go all the way through
implementation, I have no problems at all.
When I want to do a functional simulation, however, the program memory is
all zeroes. How best to go about getting the .coe data into the Foundation
functional simulator? The VHDL and verilog files reference a .mif file.
The simulator allows one to "load contents" via a hex file.
I'd prefer a solution that only requires students to edit one file to
change the program for both the hardware implementation (I've noticed that
CoreGen puts the correct data in the EDIF file) AND the simulation. It's a
pretty challenging lab as it is, without the extra pitfall of having
mismatching simulation/hardware programs.
Thanks for your time,
JP
--
Josh Pfrimmer, B.Eng.
_________________________________________
University of Victoria, ECE
jpfrimmer<AT>ece<DOT>uvic<DOT>ca
_________________________________________
->My views and opinions are not necessarily UVic's