Memory initial value

[[LinuxFc4]GaLaKtIkUs™]

I have a memory:
reg [15:0] mymem [255:0];

Ho to initialize its content?
For registers I use for example: reg [15:0] myreg=16'h3ff6;

Mehdi

 

[John_H]

[LinuxFc4]GaLaKtIkUs™ wrote:

I have a memory:
reg [15:0] mymem [255:0];

Ho to initialize its content?
For registers I use for example: reg [15:0] myreg=16'h3ff6;

Mehdi

Do you want the initialization for simulation only?
Use an initial block (Verilog basic construct).

Do you want the initialization for a specific FPGA?
There are attributes you can attach
or utilities to initialize from a file.

Do you want the initialization for an ASIC?
I can't help you here.

 

[[LinuxFc4]GaLaKtIkUs™]

John_H wrote:

GaLaKtIkUs™ wrote:
I have a memory:
reg [15:0] mymem [255:0];

Ho to initialize its content?
For registers I use for example: reg [15:0] myreg=16'h3ff6;

Mehdi

Do you want the initialization for simulation only?
Use an initial block (Verilog basic construct).

Do you want the initialization for a specific FPGA?
There are attributes you can attach
or utilities to initialize from a file.

Do you want the initialization for an ASIC?
I can't help you here.

Thanks John for your reply; here is my code, it's a dual port ram:
module dualmem(clk, ce, we, d_i, adr_i, d_o, adr_o);
input clk;
input ce;
input we;
input [7:0] d_i;
input [6:0] adr_i;
output [7:0] d_o;
input [6:0] adr_o;

reg [7:0] mem [(2**7)-1:0];

always @(posedge clk) // synchronous writeonly port
if(ce==1'b1)
if(we==1'b1)
mem[adr_i]=d_i;
assign d_o=mem[adr_o]; // asynchronous readonly port

endmodule

I'm using Xilinx Virtex-4 FPGA. this code will be synthesized as a
Distributted RAM.
By default the RAM is initialized to X by the simulator and to 0 on the
FPGA. What I would like to do is to get a 8'h10 in all positions at
initilalization, both in simulation and on the chip.

Mehdi

 

[[LinuxFc4]GaLaKtIkUs™]

[LinuxFc4]GaLaKtIkUs™ wrote:

John_H wrote:
[LinuxFc4]GaLaKtIkUs™ wrote:
I have a memory:
reg [15:0] mymem [255:0];

Ho to initialize its content?
For registers I use for example: reg [15:0] myreg=16'h3ff6;

Mehdi

Do you want the initialization for simulation only?
Use an initial block (Verilog basic construct).

Do you want the initialization for a specific FPGA?
There are attributes you can attach
or utilities to initialize from a file.

Do you want the initialization for an ASIC?
I can't help you here.

Thanks John for your reply; here is my code, it's a dual port ram:
module dualmem(clk, ce, we, d_i, adr_i, d_o, adr_o);
input clk;
input ce;
input we;
input [7:0] d_i;
input [6:0] adr_i;
output [7:0] d_o;
input [6:0] adr_o;

reg [7:0] mem [(2**7)-1:0];

always @(posedge clk) // synchronous writeonly port
if(ce==1'b1)
if(we==1'b1)
mem[adr_i]=d_i;
assign d_o=mem[adr_o]; // asynchronous readonly port

endmodule

I'm using Xilinx Virtex-4 FPGA. this code will be synthesized as a
Distributted RAM.
By default the RAM is initialized to X by the simulator and to 0 on the
FPGA. What I would like to do is to get a 8'h10 in all positions at
initilalization, both in simulation and on the chip.

Mehdi

I found the answer: the new xst (the synthesizer from xilinx) supports
initialization of type:

initial
mem[0]=8'h12; mem[1]=8'hfe; // and so on till all the momory positions
are filled

ALL the memory positions MUST be filled (initialized). If not XST will
ignore the initial block.
A loop may be used for filling blocks etc etc.

Mehdi