Memory fetch

C

Chris Maryan

Guest
In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.

Any thoughts? Thanks,

Chris
 
Chris Maryan wrote:
In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.
Click to expand...
count?

-- Mike Treseler
 
On Oct 3, 1:31 am, Chris Maryan <kmar...@gmail.com> wrote:
In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.

Any thoughts? Thanks,

Chris
Click to expand...
If you've made a read request that is still pending (i.e. the 'done'
handshake signal has not come back true) then I would think you would
nothing. Basic outline below

process(Clock)
if rising_edge(Clock) then
if (Read_Request = '1') then
if (Read_Completed = '1') then
Instruction <= Memory_Read_Data; -- Update to the new
instruction
end if;
end if;
end if;
end process;

KJ
 
Chris
Generally you tailor your CPU to the system you are building.
If this is a student project, I recommend that you tailor
your design to one of the boards that are readily available.
I like the Xilinx boards from Digilent (you need nexys or above):
http://www.digilentinc.com/
I like the Altera boards from TERASIC (DE1 is fine):
http://www.terasic.com

Keep your first version simple. Base your memory fetch time
on the actual board you decide on. That way you can test it
in system.

Cheers,
Jim
In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.

Any thoughts? Thanks,

Chris
Click to expand...
 
On Wed, 03 Oct 2007 05:31:13 -0000,
Chris Maryan <kmaryan@gmail.com> wrote:

In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.
Click to expand...
To enlarge a little on the correct but terse responses you've already
had: If you can live with the obvious performance consequences of
your CPU doing nothing whilst it's waiting for the fetch, you should
simply write the fetch controller state machine so that it remains
in its "twiddle thumbs until instruction available" state until
the memory ready signal comes true. Very vaguely, something like
this:

process (clock)
...
begin
if rising_edge(clock) then
...
case fetch_controller_state is
when need_new_instruction =>
read_request <= '1';
fetch_controller_state <= await_instruction;
when await_instruction =>
if memory_ready = '1' then
instr_buffer <= memory_data_bus;
fetch_controller_state <= start_decode;
--- else state remains at "await_instruction"
end if;
...

A related anecdote: A few years ago I did a toy CPU (mainly
to act as fodder for some of our course practicals) that used
the APB bus as its interface to memory. The original APB bus
has a fixed read cycle of exactly 2 clocks, so the instruction
fetch state machine was pretty simple and predictable. Later
I upgraded the state machine to support the newer APB3 bus,
which has a "ready" signal and can introduce wait states.
It took only about five or six lines of code to add
stall-until-ready logic in the way I've suggested. As
you might imagine, the CPU's performance is crap - but
that wasn't the point; and I suspect that for you, too, the
resulting performance is much less important than your
learning experience.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
I think you pointed me into exactly what I needed. I'm reading the Arm
(APB, etc.) bus specs at this very moment.

Sidenote: Any tips on writing the simulated memory (strictly speaking
a ROM in my case)? Especially if I want to introduce a hierarchy with
differing latencies (cache in 1 cycle, memory after some larger
delay)?

Thanks,

Chris

On Oct 6, 9:40 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Wed, 03 Oct 2007 05:31:13 -0000,

Chris Maryan <kmar...@gmail.com> wrote:
In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.

To enlarge a little on the correct but terse responses you've already
had: If you can live with the obvious performance consequences of
your CPU doing nothing whilst it's waiting for the fetch, you should
simply write the fetch controller state machine so that it remains
in its "twiddle thumbs until instruction available" state until
the memory ready signal comes true. Very vaguely, something like
this:

process (clock)
...
begin
if rising_edge(clock) then
...
case fetch_controller_state is
when need_new_instruction =
read_request <= '1';
fetch_controller_state <= await_instruction;
when await_instruction =
if memory_ready = '1' then
instr_buffer <= memory_data_bus;
fetch_controller_state <= start_decode;
--- else state remains at "await_instruction"
end if;
...

A related anecdote: A few years ago I did a toy CPU (mainly
to act as fodder for some of our course practicals) that used
the APB bus as its interface to memory. The original APB bus
has a fixed read cycle of exactly 2 clocks, so the instruction
fetch state machine was pretty simple and predictable. Later
I upgraded the state machine to support the newer APB3 bus,
which has a "ready" signal and can introduce wait states.
It took only about five or six lines of code to add
stall-until-ready logic in the way I've suggested. As
you might imagine, the CPU's performance is crap - but
that wasn't the point; and I suspect that for you, too, the
resulting performance is much less important than your
learning experience.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
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