Measuring the delay between two rising edges in modelsim sim

[Pratap]

Hi,
I want to measure the delay between two rising edges in modelsim
simulation. There are commands in spice like tools where the .measure
statements are used to measure the delays. But I am not able to find
such method, where I would fire such command to print the delays into
a text file through a tcl script.
Looking forward to some positive suggestions,
Thanks in advance,
Pratap

 

[KJ]

On Mar 25, 8:00 pm, Pratap <pratap.i...@gmail.com> wrote:

Hi,
I want to measure the delay between two rising edges in modelsim
simulation. There are commands in spice like tools where the .measure
statements are used to measure the delays. But I am not able to find
such method, where I would fire such command to print the delays into
a text file through a tcl script.
Looking forward to some positive suggestions,
Thanks in advance,
Pratap

Presuming that you know VHDL or Verilog, then write a handful of lines
of code and write the file from the simulation itself.

KJ

 

[Pratap]

On Mar 26, 7:26 am, KJ <kkjenni...@sbcglobal.net> wrote:

On Mar 25, 8:00 pm, Pratap <pratap.i...@gmail.com> wrote:

Hi,
I want to measure the delay between two rising edges in modelsim
simulation. There are commands in spice like tools where the .measure
statements are used to measure the delays. But I am not able to find
such method, where I would fire such command to print the delays into
a text file through a tcl script.
Looking forward to some positive suggestions,
Thanks in advance,
Pratap

Presuming that you know VHDL or Verilog, then write a handful of lines
of code and write the file from the simulation itself.

KJ

Can you please point me to such examples? I know VHDL...but haven't
ever tried writing to a file.

 

[Alexander Sotnikov]

On 3/26/2011 7:18 AM, Pratap wrote:

On Mar 26, 7:26 am, KJ<kkjenni...@sbcglobal.net> wrote:
On Mar 25, 8:00 pm, Pratap<pratap.i...@gmail.com> wrote:

Hi,
I want to measure the delay between two rising edges in modelsim
simulation. There are commands in spice like tools where the .measure
statements are used to measure the delays. But I am not able to find
such method, where I would fire such command to print the delays into
a text file through a tcl script.
Looking forward to some positive suggestions,
Thanks in advance,
Pratap

Presuming that you know VHDL or Verilog, then write a handful of lines
of code and write the file from the simulation itself.

KJ

Can you please point me to such examples? I know VHDL...but haven't
ever tried writing to a file.

It's just one of numerous examples that Google returns for the search
string text io vhdl:
http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm

--
Alexander

 

[Jonathan Bromley]

On Fri, 25 Mar 2011 17:00:34 -0700 (PDT), Pratap wrote:

I want to measure the delay between two rising
edges in modelsim simulation.

It really depends what you mean by "measure".

In the waveform viewer you can add a second cursor,
put your two cursors on the edges of interest and
read off the time difference in the cursor area of
the wave viewer.

In VHDL or Verilog you can, as KJ said, easily write
a piece of testbench code that waits for the first
edge, takes a copy of the current time in a variable,
waits for the second edge and then reports the
difference. In VHDL it would look something
like this:

MeasureTime: process
variable rise_A_time: time;
variable difference : time;
begin
wait until rising_edge(sigA);
rise_A_time := now;
wait until rising_edge(sigB);
difference := now - rise_A_time;
report "A-to-B time = " & time'image(difference);
wait;
end process;

If you remove the final "wait" statement, you will
get repeated reports; with the "wait" you get only
the first one.

Similarly in Verilog:

initial begin : MeasureTime
real rise_A_time;
real difference;
@(posedge sig_A) rise_A_time = $realtime;
@(posedge sig_B) difference = $realtime - rise_A_time;
$display("At time %t: A-to-B time = %t",
$realtime, difference);
end

and replace the "initial" with "always" if you want
the measurement to repeat. Learn about the $timeformat
system function in Verilog to get pretty time displays.

You could also do it in Tcl, in a simulator script,
using signal breakpoints to trigger some Tcl code
on the edges of the two signals. This, of course,
will be simulator-specific.

I guess you can see that writing it in Verilog or
VHDL code provides many opportunities for doing
much cleverer measurements, such as average or
cumulative values, jitter measurements, ratio
measurements... it's limited only by your
imagination.
--
Jonathan Bromley