M
Matt Clement
Guest
Hello
I have built both a PIC microchip controlled clock divider as well as a CPLD
clock divider in the past for various projects but was told today that a
VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
this accurate? We are looking to create a clock on the order of 10-20Khz
from something faster. We are looking to get a very low jitter output.
Anyone offer any data backing either design?
thanks
I have built both a PIC microchip controlled clock divider as well as a CPLD
clock divider in the past for various projects but was told today that a
VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
this accurate? We are looking to create a clock on the order of 10-20Khz
from something faster. We are looking to get a very low jitter output.
Anyone offer any data backing either design?
thanks