N
Noah
Guest
hi, all,
this describes a logic_vector to integer converter function.
and I comiple it in maxplusII student edition, but I found an error:
"unsupported feature error: a deferred constant declaration without a
full declaration is not supported"
but while I synthesis it in quartusII 5.1sp1, it success...
so what's wrong in maxplusII student editon? it's about packages
supported? or something else?
thanks.
follow is the code section:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vectorToInt is
port(
vector : in std_logic_vector(4 downto 0);
int : out integer range 0 to 31
);
end entity vectorToInt;
architecture behave of vectorToInt is
function VIConvert(vectorIn : std_logic_vector(4 downto 0)) return
integer is
variable intOut : integer;
variable temp : integer;
begin
intOut := 0;
for i in 0 to 4 loop
temp := 1;
if vectorIn(i) = '1' then
if i = 0 then
intOut := intOut + 1;
else
for j in 1 to i loop
temp := temp * 2;
-- since maxplusII student edition doesn't support operator
**, just use * instead here.
end loop;
intOut := intOut + temp;
end if;
elsif vectorIn(i) = '0' then
intOut := intOut;
else
intOut := 0;
end if;
end loop;
return intOut;
end function VIConvert;
signal vectorIn : std_logic_vector(4 downto 0);
begin
vectorIn <= vector;
process(vectorIn)
begin
int <= VIConvert(vectorIn);
end process;
end behave;
this describes a logic_vector to integer converter function.
and I comiple it in maxplusII student edition, but I found an error:
"unsupported feature error: a deferred constant declaration without a
full declaration is not supported"
but while I synthesis it in quartusII 5.1sp1, it success...
so what's wrong in maxplusII student editon? it's about packages
supported? or something else?
thanks.
follow is the code section:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vectorToInt is
port(
vector : in std_logic_vector(4 downto 0);
int : out integer range 0 to 31
);
end entity vectorToInt;
architecture behave of vectorToInt is
function VIConvert(vectorIn : std_logic_vector(4 downto 0)) return
integer is
variable intOut : integer;
variable temp : integer;
begin
intOut := 0;
for i in 0 to 4 loop
temp := 1;
if vectorIn(i) = '1' then
if i = 0 then
intOut := intOut + 1;
else
for j in 1 to i loop
temp := temp * 2;
-- since maxplusII student edition doesn't support operator
**, just use * instead here.
end loop;
intOut := intOut + temp;
end if;
elsif vectorIn(i) = '0' then
intOut := intOut;
else
intOut := 0;
end if;
end loop;
return intOut;
end function VIConvert;
signal vectorIn : std_logic_vector(4 downto 0);
begin
vectorIn <= vector;
process(vectorIn)
begin
int <= VIConvert(vectorIn);
end process;
end behave;