J
Jimmy
Guest
Hello all:
I am a new guy for the fpga region. I get some problem recently, is
waveform can simulate the varable which declared as "signal" in VHDL
program? I stick over there for 3 days, please advice....
I am a new guy for the fpga region. I get some problem recently, is
waveform can simulate the varable which declared as "signal" in VHDL
program? I stick over there for 3 days, please advice....