Maximum speed SPI on Spartan3a?

[atutu]

Hello,
I want to use SPI between two xilinx's FPGA, but I don't know how maximu
speed can be make communication stable?
Thanks!



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Posted through http://www.FPGARelated.com

 

[-jg]

On Nov 16, 4:14 pm, "atutu" <tuanna.hni@n_o_s_p_a_m.gmail.com> wrote:

Hello,
I want to use SPI between two xilinx's FPGA, but I don't know how maximum
speed can be make communication stable?
Thanks!

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

It will depend on the chip spacing/track length and drive/termination
you choose.

Try it and see.

There are Double and Quad bit SPI, and memory devices can go to
80MHz.Quad, or 100MHz Quad. (320-400MBd)

If you are doing full custom, and those speeds are not enough, a
Double Data rate design could double speeds.

-jg

 

[Kolja Sulimma]

On 16 Nov., 04:14, "atutu" <tuanna.hni@n_o_s_p_a_m.gmail.com> wrote:

Hello,
I want to use SPI between two xilinx's FPGA, but I don't know how maximum
speed can be make communication stable?
Thanks!

Using LVDS-Signaling and dynamic phase alignment at least 1250Mbps
should be possible in a Virtex-5 for the data pins.
However, I believe that the clock path only supports 710 MHz. As SPI
uses single data rate clocking the maximum data rate is therefore
710Mbps.

If you are communicating only with your own designs you could modify
the SPI spec to DDR to get the higher rate.

Kolja