Maximum Frequency

[knight]

Hi all,

Iam using Xilinx XST for synthesis.
Iam using almost 20 modules in my design.
each if i synthesize seperately iam getting a maximum frequency of
more than 400 Mhz. But when i combine everything iam getting
only 121Mhz.

Can you tell me the reason...???
Does this mean i cannot use a clock more than 121 Mhz in my design(iam
using and found it working well..)
How can i increase my timing for high frequencies..??
Iam providing the synthesis report here.
Can you tell me what is the Maximum frequency mentioned here..?


Timing Summary:
---------------
Speed Grade: -1

Minimum period: 8.226ns (Maximum Frequency: 121.566MHz)
Minimum input arrival time before clock: 3.043ns
Maximum output required time after clock: 3.281ns
Maximum combinational path delay: 2.072ns


I want to acheive minimum 400Mhz for my entire design.... Is it
possible...? That is my target....
Do comment...

 

[Tricky]

On Apr 2, 10:35 am, knight <krshe...@gmail.com> wrote:

Hi all,

Iam using Xilinx XST for synthesis.
Iam using almost 20 modules in my design.
each if i synthesize seperately iam getting a maximum frequency of
more than 400 Mhz. But when i combine everything iam getting
only 121Mhz.

Can you tell me the reason...???
Does this mean i cannot use a clock more than 121 Mhz in my design(iam
using and found it working well..)
How can i increase my timing for high frequencies..??
Iam providing the synthesis report here.
Can you tell me what is the Maximum frequency mentioned here..?

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 8.226ns (Maximum Frequency: 121.566MHz)
   Minimum input arrival time before clock: 3.043ns
   Maximum output required time after clock: 3.281ns
   Maximum combinational path delay: 2.072ns

I want to acheive minimum 400Mhz for my entire design.... Is it
possible...? That is my target....
Do comment...

When you only have 1 module in the design the syntheisiser has the
entire chip to put a single module in. When you put 20 together, there
is obviously more of the chip used, and depending on the connections,
the slowest time between 2 registers is 121Mhz. The timing analyser
gives you the worst case speed, ie. the largest delay over the entire
design. It may work at a higher frequency for verious reasons, but it
is best to try and obay the timing analyser. To make it clock faster,
you will have to go through and identify the slowest path, and
minimise the logic between registers.

 

[Andy]

On Apr 2, 7:35 am, Tricky <Trickyh...@gmail.com> wrote:

On Apr 2, 10:35 am, knight <krshe...@gmail.com> wrote:





Hi all,

Iam using Xilinx XST for synthesis.
Iam using almost 20 modules in my design.
each if i synthesize seperately iam getting a maximum frequency of
more than 400 Mhz. But when i combine everything iam getting
only 121Mhz.

Can you tell me the reason...???
Does this mean i cannot use a clock more than 121 Mhz in my design(iam
using and found it working well..)
How can i increase my timing for high frequencies..??
Iam providing the synthesis report here.
Can you tell me what is the Maximum frequency mentioned here..?

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 8.226ns (Maximum Frequency: 121.566MHz)
   Minimum input arrival time before clock: 3.043ns
   Maximum output required time after clock: 3.281ns
   Maximum combinational path delay: 2.072ns

I want to acheive minimum 400Mhz for my entire design.... Is it
possible...? That is my target....
Do comment...

When you only have 1 module in the design the syntheisiser has the
entire chip to put a single module in. When you put 20 together, there
is obviously more of the chip used, and depending on the connections,
the slowest time between 2 registers is 121Mhz. The timing analyser
gives you the worst case speed, ie. the largest delay over the entire
design. It may work at a higher frequency for verious reasons, but it
is best to try and obay the timing analyser. To make it clock faster,
you will have to go through and identify the slowest path, and
minimise the logic between registers.- Hide quoted text -

- Show quoted text -

Another potential reason for the difference is if your individual
blocks have combinatorial input and/or output paths (i.e. gates before
the first input register, or after the last output register) that may
not be timing constrained, because they don't fall under the nominal
clock-clock constraint when the module is synthesized by itself
(different tools handle this differently). Put that module in a larger
design, where the combinatorial output paths get tied to registered
(or worse, combinatorial) input paths on another module, and suddenly
those paths are now constrained, and start driving the overall max
clock rate.

If you have a module that has combinatorial input and/or output paths,
it is best to put it in a wrapper that inserts registers on all inputs
and outputs for performance evaluation. Note that this does not help
if your design feeds a combinatorial output from one module into a
combinatorial input on another. The propagation delays add together.
Most folks tend to avoid combinatorial outputs on modules, to avoid
instances where input and output delays sum together between modules.

Andy