Maximum Frequency

[zlotawy]

Hello,
I use Xilinx ISE. In Synthesis Report I got this message:

"Maximum Frequency: 18.019MHz".


What causes that frequency? What should I do If I would like more?


Thanks,
zlotawy

 

[KJ]

"zlotawy" <spawnek@wp.NO_SPAM.pl> wrote in message
news:febaol$367$1@inews.gazeta.pl...

Hello,
I use Xilinx ISE. In Synthesis Report I got this message:

"Maximum Frequency: 18.019MHz".


What causes that frequency?
ISE takes the VHDL code that you've written and comes up with a bitstream

that will implement the logic that you've written once it has been
downloaded into whatever device you've targeted. Inside that device there
are logic cells and flip flops and whatever the device happens to have. ISE
will also perform static timing analysis and calculate how fast the design
can be run at and still meet whatever timing requirements you may (or may
not) have specified). Generally speaking, 'maximum frequency' is talking
about the how fast two flip flops that are internal to the device can be
clocked at when implementing YOUR particular design. Other designs
implementing some totally different function may operate faster (or slower).

What should I do If I would like more?

Unless you're targetting some very old family of parts, 18 MHz is very slow

which likely means that the way you've written your code is probably not in
synchronous fashion and would likely need a massive rewrite (~100 - 200 MHz
is usually not hard to attain, but again it depends on the design and the
designer).

But as a general rule, you would use ISE to find what the slowest path are
(i.e. the ones that are limiting your design to 18 MHz) and work on
rewriting those areas to speed them up by getting rid of levels of logic and
possibly pipelining the design somewhat.

KJ