Max7000s: how to use the enable of the dffe flip-flop?

J

javid

Guest
Dear all,

I would like to register an address bus with the rising edge of the
clk and if the LOAD is '1'. Below is my VHDL code.

The problem is that when I analyse and elaborate with QII and see the
RTL view I see a mux that choose A_I or A_O with LOAD and the the
output of this mux goes to a dffe flip-flops (the output of this
flip-flops are feedback to the input of the mux). I would like to use
the enable input of the dffe flip-flops instead of the mux with the
LOAD. How to do this? is the RTL view related with what finally will
be placed and routed?.

Thanks a lot and best regards,

Javi


entity DIR_LATCH is

port( A_O: out std_logic_vector ( 18 downto 2 );
LOAD: in std_logic;
CLK_I: in std_logic;
A_I: in std_logic_vector ( 18 downto 2)
);

end entity DIR_LATCH;


-------------------------------------------------------------------------------
-- Definicion de la Arquitectura
-------------------------------------------------------------------------------

architecture DIR_LATCH_A1 of DIR_LATCH is

begin

-----------------------------------------------------------------------------
-- Definicion de la Arquitectura
-----------------------------------------------------------------------------

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2) <=
A_I( 2); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 3) <=
A_I( 3); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 4) <=
A_I( 4); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 5) <=
A_I( 5); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 6) <=
A_I( 6); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 7) <=
A_I( 7); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 8) <=
A_I( 8); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 9) <=
A_I( 9); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(10) <=
A_I(10); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(11) <=
A_I(11); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(12) <=
A_I(12); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(13) <=
A_I(13); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(14) <=
A_I(14); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(15) <=
A_I(15); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(16) <=
A_I(16); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(17) <=
A_I(17); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(18) <=
A_I(18); end if; end if;

end process ADR_REG;

end architecture DIR_LATCH_A1;
 
javid wrote:
Dear all,

I would like to register an address bus with the rising edge of the
clk and if the LOAD is '1'. Below is my VHDL code.

The problem is that when I analyse and elaborate with QII and see the
RTL view I see a mux that choose A_I or A_O with LOAD and the the
output of this mux goes to a dffe flip-flops (the output of this
flip-flops are feedback to the input of the mux). I would like to use
the enable input of the dffe flip-flops instead of the mux with the
LOAD. How to do this? is the RTL view related with what finally will
be placed and routed?.
Click to expand...
Oh my that's alot of typing (and very prone to typos). I believe the
problem is that you have more than one controlling if statement within
the process (in this case, more than one rising edge statement). But
the reality of the matter is that you only need one!


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
end if;
if( LOAD = '1' )
A_O( 3) <= A_I( 3);
end if;
.....etc....
if( LOAD = '1' )
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;

But you'll notice the load's are all the same... so why not:

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
A_O( 3) <= A_I( 3);
.....etc....
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;


But that's still WAY too much error-prone typing! In reality, we should
be using the vector form:


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(18 downto 2) <= A_I(18 downto 2);
end if;
end if;

end process ADR_REG;


If you had a real reason to not use the vector form above, you could use
a generate statement (this would allow you to optionally have a
different clock enable for each bit, if you needed that for some reason):

adr_gen : for i in 2 to 18 GENERATE

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(i) <= A_I(i);
end if;
end if;

end process ADR_REG;

end generate;



Good luck,

Marc



Thanks a lot and best regards,

Javi


entity DIR_LATCH is

port( A_O: out std_logic_vector ( 18 downto 2 );
LOAD: in std_logic;
CLK_I: in std_logic;
A_I: in std_logic_vector ( 18 downto 2)
);

end entity DIR_LATCH;


-------------------------------------------------------------------------------
-- Definicion de la Arquitectura
-------------------------------------------------------------------------------

architecture DIR_LATCH_A1 of DIR_LATCH is

begin

-----------------------------------------------------------------------------
-- Definicion de la Arquitectura
-----------------------------------------------------------------------------

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2) <=
A_I( 2); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 3) <=
A_I( 3); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 4) <=
A_I( 4); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 5) <=
A_I( 5); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 6) <=
A_I( 6); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 7) <=
A_I( 7); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 8) <=
A_I( 8); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 9) <=
A_I( 9); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(10) <=
A_I(10); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(11) <=
A_I(11); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(12) <=
A_I(12); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(13) <=
A_I(13); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(14) <=
A_I(14); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(15) <=
A_I(15); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(16) <=
A_I(16); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(17) <=
A_I(17); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(18) <=
A_I(18); end if; end if;

end process ADR_REG;

end architecture DIR_LATCH_A1;
Click to expand...
 
Thanks a lot for the comments Marc,

But my main question is that when I look at the RTL View of the vhdl
file I see that uses a D flip-flops and feedbacks the outputs of these
to the input of a mux that select with LOAD if the input to the
Dflip-flops are the previous output (A_O) or the present input (V_I).
I will use the Altera CPLD Max7000s that seems to have a D flip-flop
with enable input and I would like that the LOAD input would go to the
Enable input of the flip-flops instead of the feedback + mux solution
and leaving unconnected the enable input of the flip-flop. How to do
this?

Thanks a lot and best regards,

Javi


Marc Randolph <mrand@my-deja.com> wrote in message news:<UL6dndL0hKNIRwXdRVn-
sA@comcast.com>...
javid wrote:
Dear all,

I would like to register an address bus with the rising edge of the
clk and if the LOAD is '1'. Below is my VHDL code.

The problem is that when I analyse and elaborate with QII and see the
RTL view I see a mux that choose A_I or A_O with LOAD and the the
output of this mux goes to a dffe flip-flops (the output of this
flip-flops are feedback to the input of the mux). I would like to use
the enable input of the dffe flip-flops instead of the mux with the
LOAD. How to do this? is the RTL view related with what finally will
be placed and routed?.

Oh my that's alot of typing (and very prone to typos). I believe the
problem is that you have more than one controlling if statement within
the process (in this case, more than one rising edge statement). But
the reality of the matter is that you only need one!


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
end if;
if( LOAD = '1' )
A_O( 3) <= A_I( 3);
end if;
....etc....
if( LOAD = '1' )
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;

But you'll notice the load's are all the same... so why not:

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
A_O( 3) <= A_I( 3);
....etc....
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;


But that's still WAY too much error-prone typing! In reality, we should
be using the vector form:


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(18 downto 2) <= A_I(18 downto 2);
end if;
end if;

end process ADR_REG;


If you had a real reason to not use the vector form above, you could use
a generate statement (this would allow you to optionally have a
different clock enable for each bit, if you needed that for some reason):

adr_gen : for i in 2 to 18 GENERATE

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(i) <= A_I(i);
end if;
end if;

end process ADR_REG;

end generate;



Good luck,

Marc



Thanks a lot and best regards,

Javi


entity DIR_LATCH is

port( A_O: out std_logic_vector ( 18 downto 2 );
LOAD: in std_logic;
CLK_I: in std_logic;
A_I: in std_logic_vector ( 18 downto 2)
);

end entity DIR_LATCH;


-------------------------------------------------------------------------------
-- Definicion de la Arquitectura
-------------------------------------------------------------------------------

architecture DIR_LATCH_A1 of DIR_LATCH is

begin

-----------------------------------------------------------------------------
-- Definicion de la Arquitectura
-----------------------------------------------------------------------------

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2) <=
A_I( 2); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 3) <=
A_I( 3); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 4) <=
A_I( 4); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 5) <=
A_I( 5); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 6) <=
A_I( 6); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 7) <=
A_I( 7); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 8) <=
A_I( 8); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 9) <=
A_I( 9); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(10) <=
A_I(10); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(11) <=
A_I(11); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(12) <=
A_I(12); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(13) <=
A_I(13); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(14) <=
A_I(14); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(15) <=
A_I(15); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(16) <=
A_I(16); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(17) <=
A_I(17); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(18) <=
A_I(18); end if; end if;

end process ADR_REG;

end architecture DIR_LATCH_A1;
Click to expand...
 
javid wrote:
Thanks a lot for the comments Marc,

But my main question is that when I look at the RTL View of the vhdl
file I see that uses a D flip-flops and feedbacks the outputs of these
to the input of a mux that select with LOAD if the input to the
Dflip-flops are the previous output (A_O) or the present input (V_I).
I will use the Altera CPLD Max7000s that seems to have a D flip-flop
with enable input and I would like that the LOAD input would go to the
Enable input of the flip-flops instead of the feedback + mux solution
and leaving unconnected the enable input of the flip-flop. How to do
this?
Click to expand...
Howdy Javi,

Unless there is a very severe bug in the synthesis tools that you are
using, you do this by using one (and _only one_) "if rising_edge(clk)"
statement per process. See below for examples.

Marc


Marc Randolph <mrand@my-deja.com> wrote in message news:<UL6dndL0hKNIRwXdRVn-
sA@comcast.com>...

Oh my that's alot of typing (and very prone to typos). I believe the
problem is that you have more than one controlling if statement within
the process (in this case, more than one rising edge statement). But
the reality of the matter is that you only need one!


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
end if;
if( LOAD = '1' )
A_O( 3) <= A_I( 3);
end if;
....etc....
if( LOAD = '1' )
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;

But you'll notice the load's are all the same... so why not:

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
A_O( 3) <= A_I( 3);
....etc....
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;


But that's still WAY too much error-prone typing! In reality, we should
be using the vector form:


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(18 downto 2) <= A_I(18 downto 2);
end if;
end if;

end process ADR_REG;


If you had a real reason to not use the vector form above, you could use
a generate statement (this would allow you to optionally have a
different clock enable for each bit, if you needed that for some reason):

adr_gen : for i in 2 to 18 GENERATE

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(i) <= A_I(i);
end if;
end if;

end process ADR_REG;

end generate;


Marc

Thanks a lot and best regards,

Javi


entity DIR_LATCH is

port( A_O: out std_logic_vector ( 18 downto 2 );
LOAD: in std_logic;
CLK_I: in std_logic;
A_I: in std_logic_vector ( 18 downto 2)
);

end entity DIR_LATCH;


-------------------------------------------------------------------------------
-- Definicion de la Arquitectura
-------------------------------------------------------------------------------

architecture DIR_LATCH_A1 of DIR_LATCH is

begin

-----------------------------------------------------------------------------
-- Definicion de la Arquitectura
-----------------------------------------------------------------------------

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2) <=
A_I( 2); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 3) <=
A_I( 3); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 4) <=
A_I( 4); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 5) <=
A_I( 5); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 6) <=
A_I( 6); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 7) <=
A_I( 7); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 8) <=
A_I( 8); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 9) <=
A_I( 9); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(10) <=
A_I(10); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(11) <=
A_I(11); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(12) <=
A_I(12); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(13) <=
A_I(13); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(14) <=
A_I(14); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(15) <=
A_I(15); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(16) <=
A_I(16); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(17) <=
A_I(17); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(18) <=
A_I(18); end if; end if;

end process ADR_REG;

end architecture DIR_LATCH_A1;
Click to expand...
 
Javi,

You haven't defined your FF completely.
That's probably why you have a mux.

You should have done something like

process (clk, reset)
begin
if reset = '1' then
data <= (others => '0');
elsif clk'event and clk = '1' then
if load = '1' then
data(18 downto 2) <= data_in (..);
else
data(18 downto 2) <= (others => 'Z');
end if;
end if;
end process;

hope this helps

On 6 May 2004 02:34:00 -0700, javodv@yahoo.es (javid) wrote:

Thanks a lot for the comments Marc,

But my main question is that when I look at the RTL View of the vhdl
file I see that uses a D flip-flops and feedbacks the outputs of these
to the input of a mux that select with LOAD if the input to the
Dflip-flops are the previous output (A_O) or the present input (V_I).
I will use the Altera CPLD Max7000s that seems to have a D flip-flop
with enable input and I would like that the LOAD input would go to the
Enable input of the flip-flops instead of the feedback + mux solution
and leaving unconnected the enable input of the flip-flop. How to do
this?

Thanks a lot and best regards,

Javi


Marc Randolph <mrand@my-deja.com> wrote in message news:<UL6dndL0hKNIRwXdRVn-
sA@comct067693ast.com>...
javid wrote:
Dear all,

I would like to register an address bus with the rising edge of the
clk and if the LOAD is '1'. Below is my VHDL code.

The problem is that when I analyse and elaborate with QII and see the
RTL view I see a mux that choose A_I or A_O with LOAD and the the
output of this mux goes to a dffe flip-flops (the output of this
flip-flops are feedback to the input of the mux). I would like to use
the enable input of the dffe flip-flops instead of the mux with the
LOAD. How to do this? is the RTL view related with what finally will
be placed and routed?.

Oh my that's alot of typing (and very prone to typos). I believe the
problem is that you have more than one controlling if statement within
the process (in this case, more than one rising edge statement). But
the reality of the matter is that you only need one!


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
end if;
if( LOAD = '1' )
A_O( 3) <= A_I( 3);
end if;
....etc....
if( LOAD = '1' )
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;

But you'll notice the load's are all the same... so why not:

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O( 2) <= A_I( 2);
A_O( 3) <= A_I( 3);
....etc....
A_O(18) <= A_I(18);
end if;
end if;

end process ADR_REG;


But that's still WAY too much error-prone typing! In reality, we should
be using the vector form:


ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(18 downto 2) <= A_I(18 downto 2);
end if;
end if;

end process ADR_REG;


If you had a real reason to not use the vector form above, you could use
a generate statement (this would allow you to optionally have a
different clock enable for each bit, if you needed that for some reason):

adr_gen : for i in 2 to 18 GENERATE

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then
if( LOAD = '1' )
A_O(i) <= A_I(i);
end if;
end if;

end process ADR_REG;

end generate;



Good luck,

Marc



Thanks a lot and best regards,

Javi


entity DIR_LATCH is

port( A_O: out std_logic_vector ( 18 downto 2 );
LOAD: in std_logic;
CLK_I: in std_logic;
A_I: in std_logic_vector ( 18 downto 2)
);

end entity DIR_LATCH;


-------------------------------------------------------------------------------
-- Definicion de la Arquitectura
-------------------------------------------------------------------------------

architecture DIR_LATCH_A1 of DIR_LATCH is

begin

-----------------------------------------------------------------------------
-- Definicion de la Arquitectura
-----------------------------------------------------------------------------

ADR_REG: process ( CLK_I )
begin

if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 2) <=
A_I( 2); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 3) <=
A_I( 3); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 4) <=
A_I( 4); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 5) <=
A_I( 5); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 6) <=
A_I( 6); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 7) <=
A_I( 7); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 8) <=
A_I( 8); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O( 9) <=
A_I( 9); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(10) <=
A_I(10); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(11) <=
A_I(11); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(12) <=
A_I(12); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(13) <=
A_I(13); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(14) <=
A_I(14); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(15) <=
A_I(15); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(16) <=
A_I(16); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(17) <=
A_I(17); end if; end if;
if( rising_edge(CLK_I) ) then if( LOAD = '1' ) then A_O(18) <=
A_I(18); end if; end if;

end process ADR_REG;

end architecture DIR_LATCH_A1;
Click to expand...
 
Hey Javid,
Using Synplify? Look up syn_direct_enable in the manual.
Cheers, Syms.
 
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