MAX+plus II error:Can't interpret indexed name

[Aliki]

Hi all, I am trying to implement a simple sram in VHDL in MAX+plus II and I
get a message error:"Can't interpret indexed name", the line with the
errors is on stars...Generally there is a problem with Max plus, I can't
complile any memory when I use conv_integer or the conversion below....Can
anyone help?????


library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity sram is
port(chip_enable : in bit;
output_enable : in bit;
address : in bit_vector (3 downto 0);
data : out std_logic_vector (3 downto 0));
end sram;

architecture behaviour of sram is
constant sram_size : Integer := 15;
type sram_mem is array (0 to sram_size) of std_logic_vector (0 to
3);
signal memory : sram_mem;

begin
get_data : process(address)
begin
if (chip_enable = '0' and output_enable = '0') then
-- get data from selected address
*********data <= memory(address);**************This is the line with
the error*************
else
data <= (others => 'Z');
end if;
end process;
end behaviour;

 

[Ralf Hildebrandt]

Aliki wrote:

Hi all, I am trying to implement a simple sram in VHDL in MAX+plus II and I
get a message error:"Can't interpret indexed name", the line with the
errors is on stars...Generally there is a problem with Max plus, I can't
complile any memory when I use conv_integer or the conversion below....Can
anyone help?????

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Do you really need them - both? These are not standard libraries. use
ieee.numeric_std.all instead.

constant sram_size : Integer := 15;
type sram_mem is array (0 to sram_size) of std_logic_vector (0 to
3);
signal memory : sram_mem;

begin
get_data : process(address)

Would'nt it be better to have chip_enable and output_enable in the
sensitivity list?

*********data <= memory(address);**************This is the line with
the error*************

data is std_logic_vector (3 downto 0) and
one line of sram_mem is std_logic_vector (0 to 3)
Are you shure that you need opposite index directions?


Furthermore address has to be converted to integer, because indices are
of type integer. I guess this is the point where your compiler
complains. Think about the libraries, if you get trouble during conversions.


Ralf

 

[Mike Treseler]

Aliki wrote:

Hi all, I am trying to implement a simple sram in VHDL in MAX+plus II and

Consider using quartus.
Related threads:
http://groups.google.com/groups?q=vhdl+dpram512x1
http://groups.google.com/groups?q=vhdl+ram_32k

-- Mike Treseler

 

[LostAtC]

Try changing the line to:

data <= memory(conv_integer(address));

The index must be an integer and you've declared the address as a bit
vector.


On Tue, 24 Aug 2004 08:37:46 -0400, "Aliki" <aliki@> wrote:

Hi all, I am trying to implement a simple sram in VHDL in MAX+plus II and I
get a message error:"Can't interpret indexed name", the line with the
errors is on stars...Generally there is a problem with Max plus, I can't
complile any memory when I use conv_integer or the conversion below....Can
anyone help?????


library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity sram is
port(chip_enable : in bit;
output_enable : in bit;
address : in bit_vector (3 downto 0);
data : out std_logic_vector (3 downto 0));
end sram;

architecture behaviour of sram is
constant sram_size : Integer := 15;
type sram_mem is array (0 to sram_size) of std_logic_vector (0 to
3);
signal memory : sram_mem;

begin
get_data : process(address)
begin
if (chip_enable = '0' and output_enable = '0') then
-- get data from selected address
*********data <= memory(address);**************This is the line with
the error*************
else
data <= (others => 'Z');
end if;
end process;
end behaviour;