MAX II CPLD and I2S Clock divider jitter

[Mark]

I have MAX II CPLD with clock of 24.576 MHz as input coming from the
external crystal oscillator. This clock is used inside the CPLD to
generate sub clocks, thats no problem. Also, my design needs to output
the incoming 24.576 MHz clock as it is to the external Audio DAC
through one of the I/O pins. So I have three options. Which one is the
best option for lowest possible jitter?

1) Output the 24.576 MHz clock through one of the I/O pins that is as
close as possible to the input clock pin. This reduces the clock path.
Please correct if my assumption is wrong.
2) Use Global clock pins for clock input and output. These are
optimized for clock distribution but may have longer paths.
3) Use 1-to-2 buffer (74xxx series) after the oscillator output and
split the clock to CPLD and the DAC.


Thanks in advance
-Mark

 

[Jim Granville]

On Mar 28, 11:01 pm, Mark <markjsu...@gmail.com> wrote:

3) Use 1-to-2 buffer (74xxx series) after the oscillator output and
split the clock to CPLD and the DAC.

If you are jitter paranoid, then it is always best to avoid going
thru complex logic.

-jg

 

[Mark]

On Mar 29, 8:25 am, Jim Granville <j.m.granvi...@gmail.com> wrote:

On Mar 28, 11:01 pm, Mark <markjsu...@gmail.com> wrote:

3) Use 1-to-2 buffer (74xxx series) after the oscillator output and
split the clock to CPLD and the DAC.

 If you are jitter paranoid, then it is always best to avoid going
thru complex logic.

-jg

Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock
buffers? Is there any advantage of using clock buffers over normal
buffers for digital audio?

-Mark

 

[Jim Granville]

On Mar 29, 4:29 pm, Mark <markjsu...@gmail.com> wrote:

Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock
buffers? Is there any advantage of using clock buffers over normal
buffers for digital audio?

I've seen Single-gate logic used for this type of work.
The secret seems to be no common mode supply noise from anything other
than the clock itself.
- as any dV on a finite edge, becomes a dT aka jitter.

If you use a non inverting unit, you can design it in, and then see
if you can remove it, and measure no change

-jg

 

[Brian Drummond]

On Mon, 28 Mar 2011 21:29:47 -0700, Mark wrote:

On Mar 29, 8:25 am, Jim Granville <j.m.granvi...@gmail.com> wrote:
On Mar 28, 11:01 pm, Mark <markjsu...@gmail.com> wrote:

3) Use 1-to-2 buffer (74xxx series) after the oscillator output and
split the clock to CPLD and the DAC.

 If you are jitter paranoid, then it is always best to avoid going
thru complex logic.

-jg

Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock
buffers? Is there any advantage of using clock buffers over normal
buffers for digital audio?

Neither 74LS nor 74HC. Possibly 74AC, or purpose built clock buffers.
Fast clean edges (not HC) and full signal level switching (not LS) are
important, but watch for edges so fast they propagate right through into
the audio output.

Also, run the buffer from its own power - at least a LC Pi filter to keep
its supply quiet. (And I recommend at least the same, or separate
regulators, to keep FPGA switching noise out of the main logic supply.)

I used 74AC74 for re-clocking on an audio DAC. The effect on glitch
energy from the (R-2R ladder DAC) was noticeable, and groups of listeners
claimed to hear differences with different clock buffers (As I did). (I
started with 74F74, when I switched to 74AC they stopped sending DACs
back to the factory.) The US magazine "Stereophile" gave the result a
"Class A" rating, for what that's worth.

- Brian