matrix vs vector

[Salvatore Callea]

I've defined:

type std_logic_matrix is array (natural range <>, natural range <&gt of
std_logic;


and:

signal a : std_logic_vector(31 downto 0);
signal b : std_logic_matrix(1 to 10, 31 downto 0);


Why Modelsim report an error during compilation if I assign:

a <= b(3, 31 downto 0);

Is it posible to assign a std_logic_vector with a slice of a
std_logic_matrix in a more compact way than this:

a(0) <= b(3, 0);
a(1) <= b(3, 1);
...
a(31) <= b(3, 31);


thanks in advance: Salvatore

 

[Just an Illusion]

Hi Salvatore,

I have not try but perhaps with

a <= b(3)(31 downto 0);


JaI

Salvatore Callea wrote:

I've defined:

type std_logic_matrix is array (natural range <>, natural range <&gt of
std_logic;


and:

signal a : std_logic_vector(31 downto 0);
signal b : std_logic_matrix(1 to 10, 31 downto 0);


Why Modelsim report an error during compilation if I assign:

a <= b(3, 31 downto 0);

Is it posible to assign a std_logic_vector with a slice of a
std_logic_matrix in a more compact way than this:

a(0) <= b(3, 0);
a(1) <= b(3, 1);
...
a(31) <= b(3, 31);


thanks in advance: Salvatore

 

[Nicolas Matringe]

Just an Illusion a écrit:

Hi Salvatore,

I have not try but perhaps with

a <= b(3)(31 downto 0);

Nope, won't work either.
A matrix is not an array of vectors so you can't assign a matrix line to
a standard_logic_vector.
You can use a loop (inside a process):

process(b, index)
begin
for i in matrix'range loop -- there is a way to specify "2nd range"
a(i) <= b(index)(i); -- but I forgot it
end loop;
end process;

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Tuukka Toivonen]

In article <Xns951A8EEEB9228calleaslabenit@130.133.1.4>, Salvatore Callea wrote:

signal a : std_logic_vector(31 downto 0);
signal b : std_logic_matrix(1 to 10, 31 downto 0);

Another way to solve this is to change a matrix into array of vectors
something like this:

subtype addr_t is std_ulogic_vector(7 downto 0);
type addr_vector_t is array (integer range <&gt of addr_t;
signal ramx_ar : addr_vector_t(0 to 7);

signal x: addr_t;

then this should work:

x <= ramx_ar(4);

You can't synthesize matrices anyway, so that would be another
reason to use "array of vectors" instead of matrix.