Matlab-to-Gates for Xilinx

[Kevin Neilson]

Does Xilinx still make a Matlab (not Simulink) -to-gates tool? I don't think so, but I was just wondering. Not that I'm looking for one; I was just wondering. In theory, it would be nice, since I model most things in Matlab before writing Verilog, but such tools usually aren't great at optimizing..

 

W dniu piątek, 6 maja 2016 01:35:04 UTC+2 użytkownik Kevin Neilson napisał:
> Does Xilinx still make a Matlab (not Simulink) -to-gates tool? I don't think so, but I was just wondering. Not that I'm looking for one; I was just wondering. In theory, it would be nice, since I model most things in Matlab before writing Verilog, but such tools usually aren't great at optimizing.

Do you mean Xilinx System Generator?
I think, here you can find more info about its current state.

http://www.xilinx.com/products/design-tools/vivado/integration/sysgen.html

http://www.xilinx.com/support/documentation-navigation/design-hubs/dh0014-vivado-system-generator-hub.html


With best regard,
Wojtek

 

[Kevin Neilson]

I meant *code* conversion, not Simulink (schematic) conversion.

 

W dniu poniedziałek, 9 maja 2016 19:31:25 UTC+2 użytkownik Kevin Neilson napisał:
> I meant *code* conversion, not Simulink (schematic) conversion.

So sorry, I'm not aware of availability of such tool now.
For C written algorithms you may use their HLS.
I've used it a little, and it does its job, however the generated code is obviously not intended to be human-legible ;-).
The generated code is usually better (in terms of logic consumption and maximum clock frequency) than my "quick&dirty" VHDL solutions, but slightly worse then "thoroughly handcrafted" VHDL.

Regards,
Wojtek