Matching MIM caps

Hi,

I'm designing my first chip, that happens to be a 10-bit ADC in the
130um technology.
I need the best possible capacitor matching so I would appreciate some
advice from experienced people in this area.

In the design manual I have found the matching equation and it has two
terms: one related to the area (W*L) and another related only to the
width. It suggests that for a given capacity (area) the matching is
better if W is big and the L alone doesn't influence.

On another document I have found a graphic that shows that the quality
factor of a MIM cap increases as the L/W ratio decreases, because of
the different sheet resistances of the metal layers.

So the documentation suggests that I should use minimum L but since I
had the idea that for best matching and acurracy one should use square
capacitors I'm not sure what to do.
Is it OK to use minimum L and W = 4L or 5L?

For a 10-bit ADC the 3-sigma mismatch of two adjacent MIM caps with
the capacitance that I want is around 2.6 times bigger than what my
circuit tolerates. Should split each capacitor in 2 capacitors in
series with the double of the capacitance, to reduce further the
mismatch?

Thanks for the help,
Hugo

 

Just a small correction, instead of

Is it OK to use minimum L and W = 4L or 5L?

I would like to ask if is OK to use minimum L and W = 20L?

Thanks,
Hugo

 

[Riad KACED]

Dear Hugo,

The best matching for your ADC is the square geometry. Why ? because
the major source of mismatch in capacitors is caused by peripheral
variations. The best matching is obtained with the smallest periphery
to area ratio. The square has the lowest P/A ratio, that's why it
comes with the best matching. According to the 'Art of Analog Layout'
book : "Rectangular capacitors with moderate aspect ratios 2:1 or 3:1
can be used to construct moderately matched capacitors, but precisely
matched capacitors should be always square."
Personally, I was always using square capacitors for matching in DACs/
ADCs. W = 20L is very poor for matching as per the above explanation.
Don't bother about the 'Q' factor in your case unless your ADC is in
the range of GSPS. RF designers are those who are concerned about the
Q factor of capacitors, that's why they prefer rectangular capacitors
(They are not concerned about matching). Please look at the above
mentioned book for more tricks about capacitor matching:

http://www.amazon.com/Art-Analog-Layout-Alan-Hastings/dp/0130870617

Building up capacitor as series of bigger ones is a good idea even
though my former employer would never accept it as a solution. I mean
if the silicon area is not a problem for your IP/Design.

Hope this help !

Riad.

 

Dear Riad,

In the design manual I have the following matching expression:

M = SQT( A/(W*L)^2 + B/(W)^2 )

This is why I say that for a given area this expression gives a better
matching result for W bigger that L.
However your explanation makes sense and so I will use square
capacitors as you suggest.
Thanks again for your help!

You have already designed ADC's?
If you did, I have another question for you, even if it is for another
topic:

For a 10-bit ADC operating at 40MHz and with an input sin that has
20MHz full range, I have calculated the maximum ON resistance for the
sampling switches that charge a capacitance of 0.5pF and I arrive to
14.5 Ohm.

Since I find this value very low and I need huge transistors to get
it, I wonder if I haven't take into account something and I got a
wrong value. Does this value look reasonable to you?
I appreciate very much your help because here (at CERN) nobody has
done an ADC so nobody can help me.

Best regards,

Hugo


PS: I have ordered the book that you have recommended to me.

 

[Riad KACED]

Dear Hugo,

I'm very sorry for disappointing you but I'm lacking the necessary
skill to answer your last question. I used to design Low Drop Out
regulators myself. My ADC's knowledge is very poor. I just know the
bare minimum that helps me understanding the designers I'm asked to
support.

For more design-related questions, I would advice the Designers Guide
forum at the following location:
http://www.designers-guide.org/Forum/

I'm pretty much sure you will find somebody who's fit enough to answer
your question.

When I was designing LDOs, I have been reading the Analaog
Applications Journal from TI. It is an excellent resource to
understand the basic design practices and usually comes with many
design tips. The data converters are often discussed in this Journal.
Please give a look at:
http://www.ti.com/aaj.
I've got all the quarterly issues since 2000, I can share them if
needed.

Good luck with this !

Riad.