matched filter(root raised cosine)

[kadhiem_ayob]

A 16qam signal is upsampled by 2 and shaped by root raised cosine. At th
Rx it is matched-filtered with same rrcos filter and decimated by 2 to ge
the symbols.
All looks ok. Symbols are recovered clean.
However, the decimation leads to two phases i.e. depending on which sample
you choose from the decimator output(even or odd), only one phase is th
correct symbols. The question is: is there a way to choose even or od
correctly without eyeballing? or do we need some logic to work it out?

Regards

Kadhiem

---------------------------------------
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[kadhiem_ayob]

"kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> writes:
A 16qam signal is upsampled by 2 and shaped by root raised cosine. A
the
Rx it is matched-filtered with same rrcos filter and decimated by 2 t
get
the symbols.
All looks ok. Symbols are recovered clean.
However, the decimation leads to two phases i.e. depending on whic
samples
you choose from the decimator output(even or odd), only one phase is the
correct symbols. The question is: is there a way to choose even or odd
correctly without eyeballing? or do we need some logic to work it out?

You need some additional help to find the right phase. This can be
defined
phase reference/training symbol in regular intervals and/or by looking a
the BER
of an overlayed error correction. There are also some scrambling LFSR
that
produce multiple bits per input bit and are self synchronizing in the
descrambler. AFAIK the DSS WLAN (11Mbit) uses such a scrambler.

DVB-S demodulators try to find the sync byte pattern (0x47 every 20
bytes, the
8th sync byte is inverted) and the right FEC depuncturing setup simply b
trying
the phases and all the FEC variants. If the BER after the Reed-Solomo
decoder is
low enough and the 7*0x47+0xb8 pattern is found a few times, then a ful
lock is
assumed.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias

Many thanks Georg

already I have logic that searches for byte boundary and quadrant boundary
I never thought that matched filter need be included in the search but I
makes sense.

Kadhiem
---------------------------------------
Posted through http://www.FPGARelated.com

 

[Georg Acher]

"kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> writes:

A 16qam signal is upsampled by 2 and shaped by root raised cosine. At the
Rx it is matched-filtered with same rrcos filter and decimated by 2 to get
the symbols.
All looks ok. Symbols are recovered clean.
However, the decimation leads to two phases i.e. depending on which samples
you choose from the decimator output(even or odd), only one phase is the
correct symbols. The question is: is there a way to choose even or odd
correctly without eyeballing? or do we need some logic to work it out?

You need some additional help to find the right phase. This can be a defined
phase reference/training symbol in regular intervals and/or by looking at the BER
of an overlayed error correction. There are also some scrambling LFSRs that
produce multiple bits per input bit and are self synchronizing in the
descrambler. AFAIK the DSS WLAN (11Mbit) uses such a scrambler.

DVB-S demodulators try to find the sync byte pattern (0x47 every 204 bytes, the
8th sync byte is inverted) and the right FEC depuncturing setup simply by trying
the phases and all the FEC variants. If the BER after the Reed-Solomon decoder is
low enough and the 7*0x47+0xb8 pattern is found a few times, then a full lock is
assumed.

--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias