Mapping signals to components

[nfirtaps]

Do any timing issues occur when passing signals into components in
VHDL? I am passing some signals including a clock into my FPGA then to
a component. The component controls signals that map in and out of
pins on the FPGA. Is there any overhead or other effects I should
know about when componenitizing my VHDL code?

 

[Thomas Stanka]

Hi,

nfirtaps schrieb:

Do any timing issues occur when passing signals into components in
VHDL? I am passing some signals including a clock into my FPGA then to
a component. The component controls signals that map in and out of
pins on the FPGA. Is there any overhead or other effects I should
know about when componenitizing my VHDL code?

No, there are no timing issues.

Except for simulation purpose for not so good code.
clk2 <= clk1;
process (clk1)
A <= B;
process (clk2)
B <= A;
wont simulate as two FF changing their content on each clock cycle. The
effect is typically observable if using different component levels and
having bad code. This issue could easyly be solved by using signal
delays (A <= B after 1 ns) .

bye Thomas