Mapping of bits in Verilog !

[dash82]

Hi,

I am trying to transmit binary bits from one fpga based board to
another. For that I am generating a stream of bits and encoding it
using an encoder. The resultant encoded bits are 1 & 0 only. Now, I am
trying to modulate the bits using BPSK (binary phase shift keying). By
using BPSK, I can modulate 1 & 0 unmodulated values to be 1 & -1
modulated values respectively.

More reference for BPSK: http://en.wikipedia.org/wiki/Phase-shift_keying

I am not really sure, if this could be done in Verilog. Intutively,
this sounds simple to me that for every unmodulated '1' value, map it
to modulated '1' value and for every unmodulated '0' value, map it to
modulated '-1' value. But I am not sure if that is the right way to do
it. I am not sure how phase needs to be accounted for. Because for
BPSK, it becomes simple as there is just 180 degree phase offset.

Can anyone please guide me on performing BPSK on the bits ?

My plan is to use this BPSK bits and modulate it with Root raised
cosine filter and then transmit it.

Please point to me if I am going wrong somewhere.

Thanks.

-Shah.