Mapping FIFO into BRAM

[Beginner_Verilog]

Hello,

I have the following code for FIFO. When I try to synthesize the
verilog code on ISE targeting BRAM it throws following warning:

INFO:Xst:1788 - Unable to map block <fifo> on BRAM. Output FF <full_r>
does not have same control signals as <empty_r>.

Can anyone help me to resolve this problem?

Thanks!

Code::

module fifo(write_enb,read_enb,
data_in, data_out,
empty,full,
clk);

input clk;
input write_enb, read_enb;
input [(`WIDTH-1):0] data_in;
output [(`WIDTH-1):0] data_out;
output empty, full;

// Output registers
reg empty_r, full_r;
reg [(`WIDTH-1):0] data_out_r;

// Internal registers
integer write_ptr, read_ptr;
reg [(`WIDTH-1):0] ram [(`DEPTH-1):0];
reg do_write, do_read;

always @ (posedge clk) begin

do_read = read_enb == 1'b1 && empty == 1'b0;
do_write = write_enb == 1'b1 && full == 1'b0;

if (do_read) begin
data_out_r <= ram[read_ptr];
read_ptr <= (read_ptr + 1) % `DEPTH;
full_r <= 1'b0;
if (!do_write && (read_ptr + 1) % `DEPTH == write_ptr )
empty_r <= 1'b1;
end // if

if (do_write) begin
ram[write_ptr] = data_in;
write_ptr <= (write_ptr + 1) % `DEPTH;
empty_r <= 1'b0;
if (!do_read && read_ptr == (write_ptr + 1) % `DEPTH )
full_r <= 1'b1;
end // if

end // always

assign empty = empty_r;
assign full = full_r;
assign data_out = data_out_r;

// This should be sufficient for no Xs to leak out from ram.
initial begin
write_ptr = 1'b0;
read_ptr = 1'b0;
data_out_r = 8'b0;
empty_r = 1'b1;
full_r = 1'b0;
end
endmodule

 

[Mike Treseler]

Beginner_Verilog wrote:

INFO:Xst:1788 - Unable to map block <fifo> on BRAM. Output FF <full_r
does not have same control signals as <empty_r>.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
pg 6-18

 

[gabor]

On Apr 17, 10:10 am, Beginner_Verilog <partha.m...@gmail.com> wrote:

Hello,

I have the following code for FIFO. When I try to synthesize the
verilog code on ISE targeting BRAM it throws following warning:

INFO:Xst:1788 - Unable to map block <fifo> on BRAM. Output FF <full_r
does not have same control signals as <empty_r>.

Can anyone help me to resolve this problem?

Thanks!

Code::

module fifo(write_enb,read_enb,
            data_in, data_out,
            empty,full,
            clk);

   input clk;
   input write_enb, read_enb;
   input  [(`WIDTH-1):0] data_in;
   output [(`WIDTH-1):0] data_out;
   output empty, full;

   // Output registers
   reg                empty_r, full_r;
   reg [(`WIDTH-1):0] data_out_r;

   // Internal registers
   integer            write_ptr, read_ptr;
   reg [(`WIDTH-1):0] ram [(`DEPTH-1):0];
   reg do_write, do_read;

   always @ (posedge clk) begin

      do_read  = read_enb  == 1'b1 && empty == 1'b0;
      do_write = write_enb == 1'b1 && full  == 1'b0;

      if (do_read) begin
         data_out_r <= ram[read_ptr];
         read_ptr <= (read_ptr + 1) % `DEPTH;
         full_r <= 1'b0;
         if (!do_write && (read_ptr + 1) % `DEPTH == write_ptr )
            empty_r <= 1'b1;
      end // if

      if (do_write) begin
         ram[write_ptr] = data_in;
         write_ptr <= (write_ptr + 1) % `DEPTH;
         empty_r <= 1'b0;
         if (!do_read && read_ptr == (write_ptr + 1) % `DEPTH )
            full_r <= 1'b1;
      end // if

   end // always

   assign empty = empty_r;
   assign full  = full_r;
   assign data_out = data_out_r;

   // This should be sufficient for no Xs to leak out from ram.
   initial begin
        write_ptr = 1'b0;
        read_ptr  = 1'b0;
        data_out_r = 8'b0;
        empty_r   = 1'b1;
        full_r    = 1'b0;
   end
endmodule

I don't see why the empty or full flags should have
anything to do with creating a block RAM for the
data. The only thing I would suggest is pulling
do_read and do_write out of the always block and
just using a combinatorial assignment for them.

Generally I don't like the mixed use of blocking
and non-blocking assignments in a clocked block
if I can avoid it.

Regards,
Gabor