J
Jan
Guest
Dear all,
I have the following VHDL which gives me some problems.
entity pixel_bufferX3 is
Port (
R_0 : in STD_LOGIC_VECTOR (7 downto 0);
G_0 : in STD_LOGIC_VECTOR (7 downto 0);
B_0 : in STD_LOGIC_VECTOR (7 downto 0);
R_1 : in STD_LOGIC_VECTOR (7 downto 0);
G_1 : in STD_LOGIC_VECTOR (7 downto 0);
B_1 : in STD_LOGIC_VECTOR (7 downto 0);
R_2 : in STD_LOGIC_VECTOR (7 downto 0);
G_2 : in STD_LOGIC_VECTOR (7 downto 0);
B_2 : in STD_LOGIC_VECTOR (7 downto 0));
end pixel_bufferX3;
architecture Behavioral of pixel_bufferX3 is
component BLOCKRAM512x72
port (
dina: IN std_logic_VECTOR(71 downto 0);
end component;
begin
dp_pixbuf : BLOCKRAM512x72
port map (
dina => R_0(7 downto 0) & G_0(7 downto 0),
);
end Behavioral;
I'm trying to map all the inputs from the entity to one large bus and
map it to the dina. How to do that? Am I forced to make a local signal
and first map the inputs to that and then map dina with it?
Thank you in advance!
Regards
Jan
I have the following VHDL which gives me some problems.
entity pixel_bufferX3 is
Port (
R_0 : in STD_LOGIC_VECTOR (7 downto 0);
G_0 : in STD_LOGIC_VECTOR (7 downto 0);
B_0 : in STD_LOGIC_VECTOR (7 downto 0);
R_1 : in STD_LOGIC_VECTOR (7 downto 0);
G_1 : in STD_LOGIC_VECTOR (7 downto 0);
B_1 : in STD_LOGIC_VECTOR (7 downto 0);
R_2 : in STD_LOGIC_VECTOR (7 downto 0);
G_2 : in STD_LOGIC_VECTOR (7 downto 0);
B_2 : in STD_LOGIC_VECTOR (7 downto 0));
end pixel_bufferX3;
architecture Behavioral of pixel_bufferX3 is
component BLOCKRAM512x72
port (
dina: IN std_logic_VECTOR(71 downto 0);
end component;
begin
dp_pixbuf : BLOCKRAM512x72
port map (
dina => R_0(7 downto 0) & G_0(7 downto 0),
);
end Behavioral;
I'm trying to map all the inputs from the entity to one large bus and
map it to the dina. How to do that? Am I forced to make a local signal
and first map the inputs to that and then map dina with it?
Thank you in advance!
Regards
Jan