Map process failed

[sundar]

Problem Description:
---------------------------------------
I am using Mememc's Spartan2e-600k-LC board. My module has 2 clk
inputs.For one clk input,i am assigning the board's 100Mhz clk and the
other one i am getting from my add-on card which has serial interface
to the FPGA via GPIO pins.When i assign my clk (and some other
signals) to the GPIO pin.I am getting the following error(see error
message column).
I want to get this clk signal via the GPIO pins.Have i to enable any
clk buffer for this?If it so,where is the option to enable the clk
buffer in Xilinx ISE6.2(Project navigator) tool?Otherwise how i have
to resolve this problem?



Error Message:
---------------------------------------
1.ERROR:MapLib:93 - Illegal LOC on IPAD symbol "bitclk" or BUFGP
symbol "bitclk_BUFGP" (output signal=bitclk_BUFGP), IPAD-IBUFG should
only be LOCed to GCLKIOB site.

2.ERROR: MAP failed
Process "Map" did not complete.

I searched solution for this problem in support.xilinx.com.They
suggested to assign this to GCLK pins of sparatan2e FPGA.What to do to
assign to a GPIO pin?

1.I tried to use BUFG from UNISIM.But that time it assigns this signal
to the GCLK pin AB12.But i want to assign this Clk signal to the GPIO.

Thanks for any help..

Regards
sundar

 

[sundar]

asundar@tenet.res.in (sundar) wrote in message news:<1324caeb.0408180146.5c69e628@posting.google.com>...

Problem Description:
---------------------------------------
I am using Mememc's Spartan2e-600k-LC board. My module has 2 clk
inputs.For one clk input,i am assigning the board's 100Mhz clk and the
other one i am getting from my add-on card which has serial interface
to the FPGA via GPIO pins.When i assign my clk (and some other
signals) to the GPIO pin.I am getting the following error(see error
message column).
I want to get this clk signal via the GPIO pins.Have i to enable any
clk buffer for this?If it so,where is the option to enable the clk
buffer in Xilinx ISE6.2(Project navigator) tool?Otherwise how i have
to resolve this problem?



Error Message:
---------------------------------------
1.ERROR:MapLib:93 - Illegal LOC on IPAD symbol "bitclk" or BUFGP
symbol "bitclk_BUFGP" (output signal=bitclk_BUFGP), IPAD-IBUFG should
only be LOCed to GCLKIOB site.

2.ERROR: MAP failed
Process "Map" did not complete.

I searched solution for this problem in support.xilinx.com.They
suggested to assign this to GCLK pins of sparatan2e FPGA.What to do to
assign to a GPIO pin?

1.I tried to use BUFG from UNISIM.But that time it assigns this signal
to the GCLK pin AB12.But i want to assign this Clk signal to the GPIO.

Thanks for any help..

Regards
sundar

Hi,
I came to know that...
While receiving clk in GPIO pins, put a IBUF to receive the clk and
drive the output of IBUF to a BUFG and use the output of BUFG for your
modules.
Eg.
module m1(out,clk,reset);
....
input clk; //if you receive this on a GPIO pin.
....

IBUF b1(.I(clk),.O(tempclk));
BUFG (.I(tempclk),.O(clkout));

always @(posedge clkout)
....
....

Is there any other way of doing this?

Regards
sundar

 

[sundar]

asundar@tenet.res.in (sundar) wrote in message news:<1324caeb.0408180146.5c69e628@posting.google.com>...

Problem Description:
---------------------------------------
I am using Mememc's Spartan2e-600k-LC board. My module has 2 clk
inputs.For one clk input,i am assigning the board's 100Mhz clk and the
other one i am getting from my add-on card which has serial interface
to the FPGA via GPIO pins.When i assign my clk (and some other
signals) to the GPIO pin.I am getting the following error(see error
message column).
I want to get this clk signal via the GPIO pins.Have i to enable any
clk buffer for this?If it so,where is the option to enable the clk
buffer in Xilinx ISE6.2(Project navigator) tool?Otherwise how i have
to resolve this problem?



Error Message:
---------------------------------------
1.ERROR:MapLib:93 - Illegal LOC on IPAD symbol "bitclk" or BUFGP
symbol "bitclk_BUFGP" (output signal=bitclk_BUFGP), IPAD-IBUFG should
only be LOCed to GCLKIOB site.

2.ERROR: MAP failed
Process "Map" did not complete.

I searched solution for this problem in support.xilinx.com.They
suggested to assign this to GCLK pins of sparatan2e FPGA.What to do to
assign to a GPIO pin?

1.I tried to use BUFG from UNISIM.But that time it assigns this signal
to the GCLK pin AB12.But i want to assign this Clk signal to the GPIO.

Thanks for any help..

Regards
sundar

Hi,
I came to know that...
While receiving clk in GPIO pins, put a IBUF to receive the clk and
drive the output of IBUF to a BUFG and use the output of BUFG for your
modules.
Eg.
module m1(out,clk,reset);
....
input clk; //if you receive this on a GPIO pin.
....

IBUF b1(.I(clk),.O(tempclk));
BUFG (.I(tempclk),.O(clkout));

always @(posedge clkout)
....
....

Is there any other way of doing this?

Regards
sundar