K
Kelvin Tsai @ Singapore
Guest
Hi, all:
In my gate-level simulation without SDF, specifically for power
analysis, Verilog-XL uses the built-in delay in each gate, which
means 1ns...but the levels of some paths are bigger than my clock
rate...
In my simulation I doubled the clock period...but the toggle rate will
half...
If I write a script to divide all the "DURATION", TC0, TC1, and TX by
half, will it work correctly?
Thanks.
By the way does the "-scale " in the read_saif have anything to do
with the `timescale in my simulation? People told me he used -scale 1
and -scale 10 but got same power, so what is this -scale used for?
Best Regards,
Kelvin.
In my gate-level simulation without SDF, specifically for power
analysis, Verilog-XL uses the built-in delay in each gate, which
means 1ns...but the levels of some paths are bigger than my clock
rate...
In my simulation I doubled the clock period...but the toggle rate will
half...
If I write a script to divide all the "DURATION", TC0, TC1, and TX by
half, will it work correctly?
Thanks.
By the way does the "-scale " in the read_saif have anything to do
with the `timescale in my simulation? People told me he used -scale 1
and -scale 10 but got same power, so what is this -scale used for?
Best Regards,
Kelvin.