mandatory output binding?

[valentin tihomirov]

the outputs of a component being instantiated can be left 'open' if the
vector range is defined

entity E is
port map (
O: out std_logic_vector(1 to 10);


However, the simulatior enforces me to bind the O signal for the component
declared as:

entity E is
port map (
I: in std_logic_vector;
O: out std_logic_vector; -- assumed to be the I'range
...

e: entity E is (O => open, ) -- error here

Just a bug in my simulator?

 

[Jonathan Bromley]

On Sat, 2 Jul 2005 19:52:59 +0300, "valentin tihomirov"
<spam@abelectron.com> wrote:

However, the simulatior enforces me to bind the O signal for the component
declared as:

entity E is
port map (
I: in std_logic_vector;
O: out std_logic_vector; -- assumed to be the I'range
...

e: entity E is (O => open, ) -- error here

Just a bug in my simulator?

No, I don't think so. If you don't bind the unconstrained
array then it remains unconstrained within the entity/architecture,
and that makes no sense. For example, what would happen if you
tried to make use of "O'length" within the architecture?

By the way Valentin, I think that I and many others here would
appreciate an occasional acknowledgement of whether our
responses to you are helpful or not. Many of your questions
are quite intriguing and I'm sure people will continue to
answer them, but our answers seem to go into a black hole :-(
--
Jonathan Bromley, Consultant

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