making a glitch filter

[rajan]

Hi,

I want to have a glitch filter for 100 MHz clock and the time is 8 us
(i.e. 8 us filter). I have the following description:


signal t1 : std_ulogic; -- spike event
signal t2 : std_ulogic; -- spike event
signal t3 : std_ulogic; -- spike event
signal t4 : std_ulogic; -- spike event
signal count : unsigned(3 downto 0); -- time counter

process(reset, clk)
begin
if reset = '1' then
t1 <= (others => '0');
t2 <= (others => '0');
t3 <= (others => '0');
t4 <= (others => '0');
count <= (others => '0');

elsif clk'event and clk = '1' then
t2 <= input1; -- input port
t3 <= t2;
t4 <= t3;

if t3 = '1' then
if t4 = '0' then
count <= (others => '0');
elsif count < 15 then
count <= count+1;
else
t1 <= '1'
end if;
else
t1 <= '0';
end if;

end if;
end process;

 

[Winfried Salomon]

Hello Rajan,

"rajan" <rjnkmr10@yahoo.com> schrieb im Newsbeitrag
news:f484a14c.0503080626.1c2fa04e@posting.google.com...

Hi,

I want to have a glitch filter for 100 MHz clock and the time is 8 us
(i.e. 8 us filter). I have the following description:

I don't understand your problem description, do you mean 8e-6 s (8 us) or 8e-9 s
(8 ns)? I suppose the latter, because the 8 us filter would suppress complete
your clock.

signal t1 : std_ulogic; -- spike event
signal t2 : std_ulogic; -- spike event
signal t3 : std_ulogic; -- spike event
signal t4 : std_ulogic; -- spike event
signal count : unsigned(3 downto 0); -- time counter

process(reset, clk)
begin
if reset = '1' then
t1 <= (others => '0');
t2 <= (others => '0');
t3 <= (others => '0');
t4 <= (others => '0');
count <= (others => '0');

elsif clk'event and clk = '1' then
t2 <= input1; -- input port
t3 <= t2;
t4 <= t3;

if t3 = '1' then
if t4 = '0' then
count <= (others => '0');
elsif count < 15 then
count <= count+1;
else
t1 <= '1'
end if;
else
t1 <= '0';
end if;

end if;
end process;

I don't really understand your code, because I did not program much in VHDL. But
I designed a glitch filter some years ago and as I analyzed this problem, I
found that the only way to solve it is the use of a delay line. The delay is the
suppressing time of the glitch and multiple edges and it workes very fine in
hardware. The circuit I made is not in VHDL, but in schematics.

The problem here is: I suppose that a delay line is not good programmable in
VHDL and a delay can't be reproduced with different FPGAs. You could cascade
buffers and set attribute to "keep", but you must vary the count of them. I also
guess that this filter cannot be described in one process in VHDL at all, as you
tried it, because it is asynchronous and cannot have an external clock.

Regards, Winfried

 

[Ulf Samuelsson]

rajan wrote:

Hi,

I want to have a glitch filter for 100 MHz clock and the time is 8 us
(i.e. 8 us filter). I have the following description:


signal t1 : std_ulogic; -- spike event
signal t2 : std_ulogic; -- spike event
signal t3 : std_ulogic; -- spike event
signal t4 : std_ulogic; -- spike event
signal count : unsigned(3 downto 0); -- time counter

process(reset, clk)
begin
if reset = '1' then
t1 <= (others => '0');
t2 <= (others => '0');
t3 <= (others => '0');
t4 <= (others => '0');
count <= (others => '0');

elsif clk'event and clk = '1' then
t2 <= input1; -- input port
t3 <= t2;
t4 <= t3;

if t3 = '1' then
if t4 = '0' then
count <= (others => '0');
elsif count < 15 then
count <= count+1;
else
t1 <= '1'
end if;
else
t1 <= '0';
end if;

end if;
end process;
t1 in this code will only go high after 15 clocks high

and will go low immediately when input goes low.
This is only a glitch filter for positive glitches.


Here is a working glitch filter with test becnh for modelsim
-- **************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity filtered_io is
generic (FILTER_LENGTH : integer := 15);
port(
data : out std_logic;
input : in std_logic;
reset : in std_logic;
CLK : in std_logic
);
end filtered_io;

-- **************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
architecture rtl of filtered_io is
signal d : std_logic; -- spike event
signal shift : std_logic_vector(2 downto 0);
signal count : unsigned(4 downto 0); -- time counter

begin
process(reset, CLK,input)
begin
if reset = '1' then
shift <= (others => '0');
elsif rising_edge(clk) then
shift <= shift(1 downto 0) & input; -- input port
end if;
end process;

process(reset,clk,shift,count)
begin
if reset = '1' then
d <= '0';
count <= (others => '0');
elsif rising_edge(clk) then
if(count > FILTER_LENGTH) then
if(d = '0') then
d <= '1';
else
d <= '0';
end if;
count <= (others => '0');
elsif(shift(2) /= d) then
count <= count + 1;
d <= d;
else
count <= (others => '0');
d <= d;
end if;
end if;
end process;
data <= d;
end rtl;


Test bench
-------------

add wave -r /*
view signals
force -freeze sim:/filtered_io/clk 1 5000, 0 {10 ns} -r 40000
force -freeze sim:/filtered_io/input 0 0
force -freeze sim:/filtered_io/reset 1 0
run 10 us
force -freeze sim:/filtered_io/reset 0 0
run 10 us
force -freeze sim:/filtered_io/input 1 0
run 10 us
force -freeze sim:/filtered_io/input 0 0
run 200 ns
force -freeze sim:/filtered_io/input 1 0
run 10 us
force -freeze sim:/filtered_io/input 0 0
run 10 us
force -freeze sim:/filtered_io/input 1 0
run 200 ns
force -freeze sim:/filtered_io/input 0 0
run 10 us



--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB