Macrocell usage

[Georg Gläser]

Hi there!
How can i minimize the macrocell usage of an VHDL-Code? How can the computer
calculate the used macrocells?

Thanks,
Georg

 

[Mike Treseler]

Georg Gläser wrote:

How can i minimize the macrocell usage of an VHDL-Code?

Trial and error.

Synthesis is quite good if you follow the
recommended templates.

How can the computer
calculate the used macrocells?

The synthesizer report counts them
from the netlist it makes.
It starts with a simple netlist
of gates and flops and then fits this
as best it can into the
actual device logic cells.

-- Mike Treseler

 

[Ivan Wagner]

There are also tools that give you a graphical output of the chip's
layout and used blocks.

Some tools (Sinplify Quartus etc...) conver your VHDL code into a code
suitable for your target making everything as optimized as possible.

Cheers.