V
very_very_log
Guest
`define foo(f) f``_suffix
`define \goo* g_suffix
module abc (clk);
wire `foo(bar);
wire `\goo* ;
endmodule
`define \goo* g_suffix
module abc (clk);
wire `foo(bar);
wire `\goo* ;
endmodule
J
Jonathan Bromley
Guest
On Tue, 27 Nov 2007 01:38:27 -0800 (PST),
very_very_log <sgiitnewid@gmail.com> wrote:
macro preprocessor. (Don't get me started about
preprocessors.... when the revolution happens
and I rule the world, preprocessors will be the
first things to be ceremonially incinerated.)
Macro foo(f) has an argument f. The two
consecutive backticks in the macro body form
the "token-gluing" or concatenation operation,
allowing a macro argument to be concatenated with
a piece of plain text without any intervening
space. So
`foo(bar)
expands into
bar_suffix
The second macro falls squarely into the area
labelled Bloody Stupid in my brain. \goo* is
a Verilog escaped identifier - this works anywhere
in Verilog; any string of characters, prefixed with
backslash and terminated with whitespace, is a
legal identifier. And it's being used here as a
macro name. Why? I dunno. Madness. Anyway,
the macro invocation
`\goo*
WITH SOME TRAILING SPACE will expand into
g_suffix
If you find yourself getting excited about all
this macro business, please take a deep breath and
wait a few months until the SystemVerilog language
committees have sorted out some of the nastier
little corners associated with the relationship
between ``, string quotes and macro arguments.
Meanwhile, stick to the easy stuff - and that
certainly does NOT include macros with
escaped-identifier names
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
very_very_log <sgiitnewid@gmail.com> wrote:
It means someone's playing silly-buggers with the
macro preprocessor. (Don't get me started about
preprocessors.... when the revolution happens
and I rule the world, preprocessors will be the
first things to be ceremonially incinerated.)
Macro foo(f) has an argument f. The two
consecutive backticks in the macro body form
the "token-gluing" or concatenation operation,
allowing a macro argument to be concatenated with
a piece of plain text without any intervening
space. So
`foo(bar)
expands into
bar_suffix
The second macro falls squarely into the area
labelled Bloody Stupid in my brain. \goo* is
a Verilog escaped identifier - this works anywhere
in Verilog; any string of characters, prefixed with
backslash and terminated with whitespace, is a
legal identifier. And it's being used here as a
macro name. Why? I dunno. Madness. Anyway,
the macro invocation
`\goo*
WITH SOME TRAILING SPACE will expand into
g_suffix
If you find yourself getting excited about all
this macro business, please take a deep breath and
wait a few months until the SystemVerilog language
committees have sorted out some of the nastier
little corners associated with the relationship
between ``, string quotes and macro arguments.
Meanwhile, stick to the easy stuff - and that
certainly does NOT include macros with
escaped-identifier names
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
E
Evan Lavelle
Guest
On Tue, 27 Nov 2007 10:41:22 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:
coincidental agreement between yourself and the creator of C++
that queue[$] means nothing, and the answer to his second question is
that "the following" also means nothing.
Consider: most of the people reading this NG are presumably engineers.
They've had to learn, with great difficulty, a language which appears
to have had no decent books written about it, and which is only
documented in an LRM and a newsgroup. And now they're finding that
others are using that NG to ask incomprehensible questions about
another language which (1) will never be learnt by most of them, which
(2) has no relevance to working electronic engineers, which (3) bears
little or no resemblance to Verilog, and which (4) was created by a
desperate EDA vendor's marketing department.
Should we be encouraging this?
Evan
<jonathan.bromley@MYCOMPANY.com> wrote:
I think they're great. And I presume that this is a purely
coincidental agreement between yourself and the creator of C++
What?!! Surely the correct answer to very_very_log's first question is
that queue[$] means nothing, and the answer to his second question is
that "the following" also means nothing.
Consider: most of the people reading this NG are presumably engineers.
They've had to learn, with great difficulty, a language which appears
to have had no decent books written about it, and which is only
documented in an LRM and a newsgroup. And now they're finding that
others are using that NG to ask incomprehensible questions about
another language which (1) will never be learnt by most of them, which
(2) has no relevance to working electronic engineers, which (3) bears
little or no resemblance to Verilog, and which (4) was created by a
desperate EDA vendor's marketing department.
Should we be encouraging this?
Evan
J
Jonathan Bromley
Guest
On Tue, 27 Nov 2007 13:42:11 +0000,
Evan Lavelle <nospam@nospam.com> wrote:
[...]
finely-spun clothes for the emperor is the only
thing that offers me any chance of a reasonably
comfortable retirement. I *need* people to be
confused about SystemVerilog. My livelihood
depends on it
Unfortunately, you know what you're talking about
and it behoves me and others to listen. For sure,
you are right that SystemVerilog has [reaches for
his thesaurus] some lacunae in its specification
at this time. There are quite a few quite smart
people doing a lot of work to fix that, right now
(and a few stupid ones too - guilty as charged...).
But Verilog was in truly desperate need of updating,
and SV is a good start.... what would you prefer to
see in its place? VHDL for design and 'e' for
verification? You might have a spot of trouble with
market traction there, even though you might be
occupying the (technical) moral high ground.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Evan Lavelle <nospam@nospam.com> wrote:
[...]
Please, Evan, don't do this to me! This set of
finely-spun clothes for the emperor is the only
thing that offers me any chance of a reasonably
comfortable retirement. I *need* people to be
confused about SystemVerilog. My livelihood
depends on it
Unfortunately, you know what you're talking about
and it behoves me and others to listen. For sure,
you are right that SystemVerilog has [reaches for
his thesaurus] some lacunae in its specification
at this time. There are quite a few quite smart
people doing a lot of work to fix that, right now
(and a few stupid ones too - guilty as charged...).
But Verilog was in truly desperate need of updating,
and SV is a good start.... what would you prefer to
see in its place? VHDL for design and 'e' for
verification? You might have a spot of trouble with
market traction there, even though you might be
occupying the (technical) moral high ground.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
V
very_very_log
Guest
Boys..
that looks more to me a stage for English literature than verilog
forum.
Good discussion though !
Keep it up !
that looks more to me a stage for English literature than verilog
forum.
Good discussion though !
Keep it up !
V
very_very_log
Guest
Boys..
that looks more to me a stage for English literature than verilog
forum.
Good discussion though !
Keep it up !
that looks more to me a stage for English literature than verilog
forum.
Good discussion though !
Keep it up !
M
Mark McDougall
Guest
Jonathan Bromley wrote:
carrying any preprocessors!
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Well you'll have to go through me to get to the incinerator if you're
carrying any preprocessors!
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266