macro lvs

[tnk]

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

 

[Diva Physical Verificatio]

You have to have both the layout and schematic stop netlisting at the
same level of detail. The detail level of the layout is controlled by
how you extract. Flat gets you transistors and such. Macro gets you
logic blocks (macro cells). When you extract with macro cells, you also
have to have the schematic netlisting treat the equivalent symbols as
leaf nodes of the netlist. Usually you use macro cell mode because there
are no schematics to go with the low level symbols, so the level of
detail is not at the transistors.

I would say that your schematics expand all the way down to transistors,
which causes LVS to compare transistors to macro cells.

On 1 Sep 2004 21:08:58 -0700, tnk11@yahoo.com (tnk) wrote:

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

 

[tnk]

actually I imported the schematic from verilog file and I have every
symbols view. What I want is hierarchical hspice file of layout. Is
there any way to stop the schematics expanding all the way down to
transistors level? I thought by setting macro LVS will do the trick,
but pratically it is not...

tnk


Diva Physical Verification <diva@cadence.com> wrote in message news:<qhbdj0lvqgvv9448pphmjg0dgmkfblfdk5@4ax.com>...

You have to have both the layout and schematic stop netlisting at the
same level of detail. The detail level of the layout is controlled by
how you extract. Flat gets you transistors and such. Macro gets you
logic blocks (macro cells). When you extract with macro cells, you also
have to have the schematic netlisting treat the equivalent symbols as
leaf nodes of the netlist. Usually you use macro cell mode because there
are no schematics to go with the low level symbols, so the level of
detail is not at the transistors.

I would say that your schematics expand all the way down to transistors,
which causes LVS to compare transistors to macro cells.

On 1 Sep 2004 21:08:58 -0700, tnk11@yahoo.com (tnk) wrote:

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

 

[Andrew Beckett]

It's probably a matter of arranging a switch/stop list for Diva LVS netlisting
so that it stops at the gate level.

Take a look at the example .simrc file in <instdir>/tools/dfII/cdsuser
and look for lvsSchematicStopList - you can set these variables in your
own .simrc file to override the default. Of course, there would need to be
some sort of view at the level you want to stop at (and this view must
be in both the switch (lvsSchematicViewList) and the stop list
(lvsSchematicStopList) for it to stop there. Also, the lvsSchematicViewList
(like other view switch lists in DFII netlisting) is searched in order from
left to right, descending into the first view it finds in that list for each
cell.

Regards,

Andrew.

On 2 Sep 2004 05:04:50 -0700, tnk11@yahoo.com (tnk) wrote:

actually I imported the schematic from verilog file and I have every
symbols view. What I want is hierarchical hspice file of layout. Is
there any way to stop the schematics expanding all the way down to
transistors level? I thought by setting macro LVS will do the trick,
but pratically it is not...

tnk


Diva Physical Verification <diva@cadence.com> wrote in message news:<qhbdj0lvqgvv9448pphmjg0dgmkfblfdk5@4ax.com>...
You have to have both the layout and schematic stop netlisting at the
same level of detail. The detail level of the layout is controlled by
how you extract. Flat gets you transistors and such. Macro gets you
logic blocks (macro cells). When you extract with macro cells, you also
have to have the schematic netlisting treat the equivalent symbols as
leaf nodes of the netlist. Usually you use macro cell mode because there
are no schematics to go with the low level symbols, so the level of
detail is not at the transistors.

I would say that your schematics expand all the way down to transistors,
which causes LVS to compare transistors to macro cells.

On 1 Sep 2004 21:08:58 -0700, tnk11@yahoo.com (tnk) wrote:

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd