lwIP RAW mode support for V4 temac

P

Patrick Dubois

Guest
Hello,

Does anyone know of an example using lwIP in RAW mode with the
Virtex-4 temac? From what I understand, the lwIP temac port seemingly
only supports lwIP in sockets mode with xilkernel.

I don't quite understand the lack of temac support at the software
level. What are people doing when using temac on the V4? Is everyone
using lwIP in sockets mode? No one is using raw lwIP on the V4?

Patrick
 
On 4 May, 01:31, Patrick Dubois <prdub...@gmail.com> wrote:
What are people doing when using temac on the V4? Is everyone
using lwIP in sockets mode?
Click to expand...
I use sockets.

Cheers,
Jon
 
Patrick Dubois wrote:
Hello,

Does anyone know of an example using lwIP in RAW mode with the
Virtex-4 temac? From what I understand, the lwIP temac port seemingly
only supports lwIP in sockets mode with xilkernel.

I don't quite understand the lack of temac support at the software
level. What are people doing when using temac on the V4? Is everyone
using lwIP in sockets mode? No one is using raw lwIP on the V4?
At X-Fest they said that raw mode will be available with EDK9.2, which
Click to expand...
is supposed to be available sometime after ISE9.2, which is scheduled
for September, IIRC.

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...
 
On May 5, 6:36 am, Sean Durkin <news_ma...@durkin.de> wrote:

At X-Fest they said that raw mode will be available with EDK9.2, which
is supposed to be available sometime after ISE9.2, which is scheduled
for September, IIRC.
Click to expand...
Thanks for the info. Unfortunately September is a little too late in
my case...

Patrick
 
On May 4, 2:31 am, Patrick Dubois <prdub...@gmail.com> wrote:
Hello,

Does anyone know of an example using lwIP in RAW mode with the
Virtex-4 temac? From what I understand, the lwIP temac port seemingly
only supports lwIP in sockets mode with xilkernel.

I don't quite understand the lack of temac support at the software
level. What are people doing when using temac on the V4? Is everyone
using lwIP in sockets mode? No one is using raw lwIP on the V4?

Patrick
Click to expand...
Why do you need a RAW mode? Do you actually need a TCP/IP stack? If
not you can write directly to TEMAC and send RAW frames at highest
speed possible.

Guru
 
"Patrick Dubois" wrote:

Does anyone know of an example using lwIP in RAW mode with the
Virtex-4 temac? From what I understand, the lwIP temac port seemingly
only supports lwIP in sockets mode with xilkernel.
Click to expand...
If you browse to my website at www.paultobias.com/Xilinx, I have posted the
source to a
LWIP driver and startup code for a raw API TCP client application that runs
on the V4fx ML403 board on top of Xilkernel (though it could be just as
easily standalone at present.)

LWIP using sockets was far too slow for us, so I put this together using the
Temac sockets code for EDK 8.2/9.1 and the emac raw api driver (I think for
an older EDK version).
So far this is tested only for receiving TCPIP packets, which it does at
3-400 Mbps, which is in
line with Ron Wright's presentation at Xfest recently. Using a good 32 bit
memory aligned memcpy function instead of the many bytewise packet copies in
LWIP should be an easy
first step to improve this rate.

You are welcome to use this as a starting point, but be aware that I am a
novice at LWIP, TCP/IP internals and Xilinx, and the output routines are
totally untried or tested, except for
those used by the lower levels (ARP and ACKs etc.). More info in the
ReadMe file on site.

Paul

www.paultobias.com
 
On May 8, 10:29 pm, "Paul Tobias" <PaulTob...@MyWebSite.com> wrote:
"Patrick Dubois" wrote:
Does anyone know of an example using lwIP in RAW mode with the
Virtex-4 temac? From what I understand, the lwIP temac port seemingly
only supports lwIP in sockets mode with xilkernel.

If you browse to my website atwww.paultobias.com/Xilinx, I have posted the
source to a
LWIP driver and startup code for a raw API TCP client application that runs
on the V4fx ML403 board on top of Xilkernel (though it could be just as
easily standalone at present.)

LWIP using sockets was far too slow for us, so I put this together using the
Temac sockets code for EDK 8.2/9.1 and the emac raw api driver (I think for
an older EDK version).
So far this is tested only for receiving TCPIP packets, which it does at
3-400 Mbps, which is in
line with Ron Wright's presentation at Xfest recently. Using a good 32 bit
memory aligned memcpy function instead of the many bytewise packet copies in
LWIP should be an easy
first step to improve this rate.

You are welcome to use this as a starting point, but be aware that I am a
novice at LWIP, TCP/IP internals and Xilinx, and the output routines are
totally untried or tested, except for
those used by the lower levels (ARP and ACKs etc.). More info in the
ReadMe file on site.

Paul

www.paultobias.com
Click to expand...
Ave Paul!
There is a lack of fast and free TCP/IP stacks which work with TEMAC.
It would be nice to port your stack to GSRD design (www.xilinx.com/
gsrd) to get a maximum speed and royalty free reference design.
I got this design working on Avnet Virtex-4FX12 MiniModule, which is a
low cost high performance OEM module.
Unfortunatelly there are no good reference designs which can exploit
this performance. If I were a better SW engineer I could help you on
development from which both would benefit.

Guru
 
On May 8, 4:50 am, Guru <ales.gor...@email.si> wrote:
Why do you need a RAW mode? Do you actually need a TCP/IP stack? If
not you can write directly to TEMAC and send RAW frames at highest
speed possible.

Guru
Click to expand...
Well, we need to send data using the TCP protocol ideally, but the UDP
protocol could work as well. So my understanding is that a TCP/IP
stack is required in our case. Maybe we could construct our own UDP
packets without a stack though...

RAW mode is simply to acheive better performance than sockets mode and
also to ease the development (we don't want to bother with an OS and
threads).

Thanks.

Patrick
 
On May 8, 4:29 pm, "Paul Tobias" <PaulTob...@MyWebSite.com> wrote:
If you browse to my website atwww.paultobias.com/Xilinx, I have posted the
source to a
LWIP driver and startup code for a raw API TCP client application that runs
on the V4fx ML403 board on top of Xilkernel (though it could be just as
easily standalone at present.)

LWIP using sockets was far too slow for us, so I put this together using the
Temac sockets code for EDK 8.2/9.1 and the emac raw api driver (I think for
an older EDK version).
So far this is tested only for receiving TCPIP packets, which it does at
3-400 Mbps, which is in
line with Ron Wright's presentation at Xfest recently. Using a good 32 bit
memory aligned memcpy function instead of the many bytewise packet copies in
LWIP should be an easy
first step to improve this rate.

You are welcome to use this as a starting point, but be aware that I am a
novice at LWIP, TCP/IP internals and Xilinx, and the output routines are
totally untried or tested, except for
those used by the lower levels (ARP and ACKs etc.). More info in the
ReadMe file on site.

Paul

www.paultobias.com
Click to expand...
Thanks a lot Paul. Your XTemacif.c driver is exactly what is needed
(which should have been provided by Xilinx in the first place). I
didn't feel like I had the knowledge to write it myself, thanks for
sharing your code!

Patrick
 
Guru wrote:
Ave Paul! There is a lack of fast and free TCP/IP stacks which work
with TEMAC. It would be nice to port your stack to GSRD design
(www.xilinx.com/ gsrd) to get a maximum speed and royalty free
reference design. I got this design working on Avnet Virtex-4FX12
MiniModule, which is a low cost high performance OEM module.
Unfortunatelly there are no good reference designs which can exploit
this performance. If I were a better SW engineer I could help you on
development from which both would benefit.

Guru
Click to expand...

Hi Guru,

I am the hardware engineer who is working with Paul. I'd love to hear
any comments you might have on our approach.

Our application specific IP that must also fit in the FPGA is a PLB
master DMA device that uses about 50% of the BRAM and 25% of the fabric
in the FX12. We originally were going to use the FX12 Minimodule, but
switched to the ML403 to get 2x the DDR bandwidth. We can get by with
400 Mb/s performance for now, but would like to get 800 Mb.

It seemed like all the GSRD examples almost filled a FX12, particularly
with BRAM usage, so we used the EDK supplied PLB TEMAC core and the PLB
DDR controller for now.

Since our app only needs high speed in the receive direction, it seemed
like it should be possible to remove half the GSRD logic (i.e. the
transmit part) and then everything would fit. As someone who has worked
with the GSRD, do you have a feel for how hard this would be? Or would
you guess the full GSRD (both directions) could fit with our IP somehow?
The critical resource seems to be BRAM and it always seemed like the
xilinx IP really used more BRAM that it should.

thanks,
Jeff
 
On May 9, 7:16 pm, Jeff Cunningham <j...@sover.net> wrote:
Guru wrote:

Ave Paul! There is a lack of fast and free TCP/IP stacks which work
with TEMAC. It would be nice to port your stack to GSRD design
(www.xilinx.com/gsrd) to get a maximum speed and royalty free
reference design. I got this design working on Avnet Virtex-4FX12
MiniModule, which is a low cost high performance OEM module.
Unfortunatelly there are no good reference designs which can exploit
this performance. If I were a better SW engineer I could help you on
development from which both would benefit.

Guru

Hi Guru,

I am the hardware engineer who is working with Paul. I'd love to hear
any comments you might have on our approach.

Our application specific IP that must also fit in the FPGA is a PLB
master DMA device that uses about 50% of the BRAM and 25% of the fabric
in the FX12. We originally were going to use the FX12 Minimodule, but
switched to the ML403 to get 2x the DDR bandwidth. We can get by with
400 Mb/s performance for now, but would like to get 800 Mb.

It seemed like all the GSRD examples almost filled a FX12, particularly
with BRAM usage, so we used the EDK supplied PLB TEMAC core and the PLB
DDR controller for now.

Since our app only needs high speed in the receive direction, it seemed
like it should be possible to remove half the GSRD logic (i.e. the
transmit part) and then everything would fit. As someone who has worked
with the GSRD, do you have a feel for how hard this would be? Or would
you guess the full GSRD (both directions) could fit with our IP somehow?
The critical resource seems to be BRAM and it always seemed like the
xilinx IP really used more BRAM that it should.

thanks,
Jeff
Click to expand...
Jeff,

My GSRD design uses about 70% of FX12 logic resources and about 60% of
BRAMs. BRAM usage is easy to control since you can set FIFO size from
1BRAM for a MPMC2 port. The best of MPMC2 is an NPI port which
simplifies the user peripherals with DMA - what I use for image
acquisition. I also tested TEMAC transfer rates to the PC: 730Mbit
1.5k MTU and 850Mbit for 7k MTU.
If you need any additional resources do not hesiste to contact me.

Guru
 
Hi, I'm trying to transfer a small .bin file of size utmost 1-2MB from PC to sdr ddrram of ML403 using a crossover Ethernet cable (TCP/IP). I'm using PowerPC and plb bus. How do I write a socket program to transfer the file?
 
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