M
meghna
Guest
Hi,
I am using Virtuoso tool of Cadence to run the LVS. I am getting
'Analysis Job Failed' error.
In the LVS directory, no netlist is getting generated. The 'si.log' file
has following global error -
Cannot find switch master cell for instance M14 in cellView
(inverter_adc_lvs schematic) from viewlist 'lvs schematic gate_sch
cmos_sch '
and similar errors for every transistor.
If someone knows the solution, please reply soon.
Thanks!
I am using Virtuoso tool of Cadence to run the LVS. I am getting
'Analysis Job Failed' error.
In the LVS directory, no netlist is getting generated. The 'si.log' file
has following global error -
Cannot find switch master cell for instance M14 in cellView
(inverter_adc_lvs schematic) from viewlist 'lvs schematic gate_sch
cmos_sch '
and similar errors for every transistor.
If someone knows the solution, please reply soon.
Thanks!