LVS question about layout label on internal nets

In my previous experience, when I run LVS with Calibre, it only allows
labels on ports in the layout. If I put a label on an internal net,
then LVS would report error. But if I run LVS with Hercules, then it
does not care whether there's any label on internal nets.

Is this determined by the tool? Or are there any options that allow us
to configure this? If there's such options, would you please show me
how to use it?

Thank you in advance.

 

[vtcad]

On Nov 28, 7:38 am, chen_zhi...@yahoo.com wrote:

In my previous experience, when I run LVS with Calibre, it only allows
labels on ports in the layout. If I put a label on an internal net,
then LVS would report error. But if I run LVS with Hercules, then it
does not care whether there's any label on internal nets.

Is this determined by the tool? Or are there any options that allow us
to configure this? If there's such options, would you please show me
how to use it?

Thank you in advance.

there are options that can be set inside of the Calibre code. You can
specify what layer Port labels are on, and what layer internal nets
are labeled on, so it knows how to extract them.

 

there are options that can be set inside of the Calibre code. You can
specify what layer Port labels are on, and what layer internal nets
are labeled on, so it knows how to extract them.

Hi, thank you. Would you please explain how to use these kind of
options in Calibre? And how about Hercules?

What's more, the internal net labels and port labels are usually on
the same set of layers. So they usually cannot be identified according
to the layer. Is there any approach to identify ports and internal
nets on the same layer?