LVS problems with Assura

[Bea]

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

 

[Andrew Beckett]

On 20 Feb 2006 07:45:58 -0800, "Bea" <beatriz.olleta@gmail.com> wrote:

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

I've seen this problem where a customer had used POLY1/pin for one of the pins -
and the Assura rules are not taking any notice of anything other thant he
metal*/pin layers.

Could that be it?

Are you doing the LVS from a DFII database or GDSII?

Regards,

Andrew.

 

[Bea]

Hello Andrew,

Yes, that was it!!!!! I had a poly pin and that was causing all the
errors. Thank you very much for your help

Beatriz

Andrew Beckett wrote:

On 20 Feb 2006 07:45:58 -0800, "Bea" <beatriz.olleta@gmail.com> wrote:

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

I've seen this problem where a customer had used POLY1/pin for one of the pins -
and the Assura rules are not taking any notice of anything other thant he
metal*/pin layers.

Could that be it?

Are you doing the LVS from a DFII database or GDSII?

Regards,

Andrew.

 

در دوشنبه 20 فوریهٔ 2006، ساعت 19:15:58 (UTC+3:30)، Bea نوشته:

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

در دوشنبه 20 فوریهٔ 2006، ساعت 19:15:58 (UTC+3:30)، Bea نوشته:

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

در دوشنبه 20 فوریهٔ 2006، ساعت 19:15:58 (UTC+3:30)، Bea نوشته:

Hello,

We just started using this new design kit for TSMC18 RF process. We
made the schematic and symbol views in Cadence for an inverter and a
layout view as well using p-cells. We were able to run simulations with
the schematic and use Assura to DRC the layout. However, we are
experiencing some technical difficulty to run an LVS with Assura.

More specifically, LVS would fail due to "unbounded devices" errors on
pmos2v and nmos2v. We were able to get around that by setting ":gen:
abortOnUnboundDevices( nil )" in avCompareRules so that it does not
stop on unbound devices. Then it does not recognize the pins in the
layout and complains that all the pins on the same layer (e.g., metal1
pn) are shorted together. We also tried different pin types (symbolic
and shape), but that didn't make any difference. In fact, we don't
think Assura recognized any pins in the layout at all.

If anyone has any idea what's causing the problem, please let us know.
We would appreciate it very much. By the way, we are using Assura 3.15
(we also tried with Assura 3.13USR1, but same errors) and ICFB
5033USR2.

Bea

Hello.
I have the same problem with assura Lvs. in extraction part all paths are reported short circuit while all reported nets should be connected to each other and actually all pins are reported as unbound pins. all pins are in metal1.pn and I have no Polly pin.previous parts of the circuit was matched successfully but in this step, this problem arose.
any help will be appreciated very much.

Noushin Davari