LVS problem

[Kuan Zhou]

Hi,

I have a huge layout now. The LVS takes a really really long time to
finish. Is there any ways to speed it up? Can LVS igore some blocks in the
layout and only check the rest of the entire layout? Can it be done in the
hierarchy editor?

Thank you very much!

Kuan

 

[Andrew Beckett]

On Fri, 22 Apr 2005 00:37:11 -0400, Kuan Zhou <koy2@cisunix.unh.edu> wrote:

Hi,

I have a huge layout now. The LVS takes a really really long time to
finish. Is there any ways to speed it up? Can LVS igore some blocks in the
layout and only check the rest of the entire layout? Can it be done in the
hierarchy editor?

Thank you very much!

Kuan

Kuan,

It's important you say which LVS tool you're using. Any answer is likely to be
different depending on which verification tool set you're using.

It could be Diva, Dracula, Assura, Calibre, Hercules or others...

Regards,

Andrew.

 

[Kuan Zhou]

Hi,

I am using Diva. I also have Assura available. Sorry for the
confusion.

Kuan

On Fri, 22 Apr 2005, Andrew Beckett wrote:

On Fri, 22 Apr 2005 00:37:11 -0400, Kuan Zhou <koy2@cisunix.unh.edu> wrote:

Hi,

I have a huge layout now. The LVS takes a really really long time to
finish. Is there any ways to speed it up? Can LVS igore some blocks in the
layout and only check the rest of the entire layout? Can it be done in the
hierarchy editor?

Thank you very much!

Kuan

Kuan,

It's important you say which LVS tool you're using. Any answer is likely to be
different depending on which verification tool set you're using.

It could be Diva, Dracula, Assura, Calibre, Hercules or others...

Regards,

Andrew.

 

[Kuan Zhou]

Hi,

But I have around 1 million transsitors. Even Assura I guess will take
a long time to finish.
When I thought is to ask the LVS tool to ignore some blocks in the LVS
if these blocks have been proved to be correct. The LVS tool will only
use the pins in these blocks for checking. I am not sure whether it's
doable because seems nobody did such a huge layout before. I am wondering
how CPU is designed. Intel never does LVS on the top level design?

Kuan

On Fri, 22 Apr 2005 jayl-news@accelerant.net wrote:

Kuan Zhou wrote:
I am using Diva. I also have Assura available.

I have a huge layout now. The LVS takes a really really long
time to
finish. Is there any ways to speed it up? Can LVS igore some
blocks in the
layout and only check the rest of the entire layout? Can it be
done in the
hierarchy editor?

If you have Assura available, that is surely the way to
go. If your hierarchy is at all reasonable, your LVS
(and DRC) will be many times faster than Diva, without
ignoring any data.

-Jay-

 

[Richard Griffith]

When I thought is to ask the LVS tool to ignore some blocks in the
LVS if these blocks have been proved to be correct.

That is very trusting in that everything is fine and none of the other
blocks have a stray piece that lies over one of the already verified
blocks. Just run the hierarchical checker and let it use the figure
bounding boxes to limit searches.

Always do fill at the lowest possible level to help the hierarchical
tools work well.




----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
----= East and West-Coast Server Farms - Total Privacy via Encryption =----

 

[G Vandevalk]

Run macro LVS.

(carefully in sync with macro extract
... and then only to fix the lower level lvs issues
.... then run flat!)

Note that in macro extract, you need to create pins.
You can override the macro with properties (RTM)

You must exactly match the hierachy at the levels you describe.

and remember that Cadence Extract does not catch connectivity across
the hierachy except at pins. (Which is why you run flat a the end)

-- G


"Kuan Zhou" <koy2@cisunix.unh.edu> wrote in message
newsine.LNX.4.62.0504220032360.31094@pascal.unh.edu...

Hi,

I have a huge layout now. The LVS takes a really really long time to
finish. Is there any ways to speed it up? Can LVS igore some blocks in the
layout and only check the rest of the entire layout? Can it be done in the
hierarchy editor?

Thank you very much!

Kuan

 

[Andrew Beckett]

Hi Kuan,

But Assura will take advantage of the hierarchy to avoid repeating checks
on cells already checked.

A million transistors is an awful lot for Diva!

Andrew.

On Sun, 24 Apr 2005 13:42:28 -0400, Kuan Zhou <koy2@cisunix.unh.edu> wrote:

Hi,

But I have around 1 million transsitors. Even Assura I guess will take
a long time to finish.
When I thought is to ask the LVS tool to ignore some blocks in the LVS
if these blocks have been proved to be correct. The LVS tool will only
use the pins in these blocks for checking. I am not sure whether it's
doable because seems nobody did such a huge layout before. I am wondering
how CPU is designed. Intel never does LVS on the top level design?

Kuan

On Fri, 22 Apr 2005 jayl-news@accelerant.net wrote:


Kuan Zhou wrote:
I am using Diva. I also have Assura available.

I have a huge layout now. The LVS takes a really really long
time to
finish. Is there any ways to speed it up? Can LVS igore some
blocks in the
layout and only check the rest of the entire layout? Can it be
done in the
hierarchy editor?

If you have Assura available, that is surely the way to
go. If your hierarchy is at all reasonable, your LVS
(and DRC) will be many times faster than Diva, without
ignoring any data.

-Jay-

 

Kuan Zhou wrote:

I am using Diva. I also have Assura available.

I have a huge layout now. The LVS takes a really really long
time to
finish. Is there any ways to speed it up? Can LVS igore some
blocks in the
layout and only check the rest of the entire layout? Can it be
done in the
hierarchy editor?

If you have Assura available, that is surely the way to
go. If your hierarchy is at all reasonable, your LVS
(and DRC) will be many times faster than Diva, without
ignoring any data.

-Jay-

 

Kuan Zhou wrote:

But I have around 1 million transistors. Even Assura I guess will
take
a long time to finish.

The last time I taped out a chip that small with Assura, the LVS run
time for full-chip was 30 minutes (2.4 GHz P4, Linux).

The stuff I'm doing recently is about 5M transistors, LVS run time
about 105 minutes (2.8GHz Xeon, Linux).

FWIW, I did tape out 1M transistors in Diva, once, years ago in
..25um. LVS runtime was about 20 hours (750MHz USIII). We were
very grateful it ran to completion.

When I thought is to ask the LVS tool to ignore some blocks in
the LVS
if these blocks have been proved to be correct. The LVS tool will
only
use the pins in these blocks for checking. I am not sure whether it's

doable because seems nobody did such a huge layout before.

"Blackbox" LVS is doable in Diva (I've never done it myself) and
straightforward in Assura (I have done it there, in situations
where the contents of said box didn't exist yet!).

If you have Assura, and any reasonable hierarchy in your design
at all, you're in good shape. 1M transistors is medium-sized.

-Jay-