LVS on Encounter generated layout

[pdw]

Hello,
I have some standard-cell logic I want to add to an analog circuit. I
generated the standard-cell layout using SoC Encounter and have
imported it into Cadence.

Is it possible to create a symbol view corresponding to the layout
(according to the Verilog code), so I can add this symbol in my
schematic and run a LVS for the complete system?

Thanks a lot,
Pieter

 

[pdw]

Hi Riad,
thanks for your quick response!

This cdl netlist, where can I find this? Is it generated by Encounter?
Or do I need to export it from Synopsys DC? (As you see, this is the
first time I do a std cell design...)

What I ideally want, is the Verilog functional view, layout and symbol
view associated with the same circuit.

Regards,
Pieter


On Aug 25, 8:53 am, Riad KACED <riad.ka...@gmail.com> wrote:

On Aug 25, 7:43 am, pdw <dewit.pie...@gmail.com> wrote:

Hello,
I have some standard-cell logic I want to add to an analog circuit. I
generated the standard-cell layout using SoC Encounter and have
imported it into Cadence.

Is it possible to create a symbol view corresponding to the layout
(according to the Verilog code), so I can add this symbol in my
schematic and run a LVS for the complete system?

Thanks a lot,
Pieter

Ciao Pieter,

Yes of course it is possible.
You just need to include the cdl netlist corresponding to your digital
when running your Assura/Calibre LVS. Simple as that ;-)

Cheers,
Riad.

 

[Riad KACED]

On Aug 25, 8:00 am, pdw <dewit.pie...@gmail.com> wrote:

Hi Riad,
thanks for your quick response!

This cdl netlist, where can I find this? Is it generated by Encounter?
Or do I need to export it from Synopsys DC? (As you see, this is the
first time I do a std cell design...)

What I ideally want, is the Verilog functional view, layout and symbol
view associated with the same circuit.

Regards,
Pieter

On Aug 25, 8:53 am, Riad KACED <riad.ka...@gmail.com> wrote:

On Aug 25, 7:43 am, pdw <dewit.pie...@gmail.com> wrote:

Hello,
I have some standard-cell logic I want to add to an analog circuit. I
generated the standard-cell layout using SoC Encounter and have
imported it into Cadence.

Is it possible to create a symbol view corresponding to the layout
(according to the Verilog code), so I can add this symbol in my
schematic and run a LVS for the complete system?

Thanks a lot,
Pieter

Ciao Pieter,

Yes of course it is possible.
You just need to include the cdl netlist corresponding to your digital
when running your Assura/Calibre LVS. Simple as that ;-)

Cheers,
Riad.

Ciao Pieter,

Both Calibre/Assura can be used for LVS with a gate level Verilog
netlist. You can use that Verilog netlist for your block. The CDL
netlist I'm talking about is the one defining the primitives of the
gates. This CDL netlist should be provided by your PDK/Foundry/
DigitalLib provider.

If you are interested in CDL netlisting:

1. I'm pretty much sure your digital tool is able to export a cdl
netlist. Usually, the digital blocks come with a layout, a structural/
functional HDL and often the CDL netlist. My guess is that digital
tools are able to export CDLs but my knowledge in there (Digital BE)
is very weak I'm afraid :-(

2. If not, then you can import your verilog in DFII using Otherwise
you can do this by using CIW->File->Import->Verilog. This will make a
schematic of your design and you don't need any CDL netlist for the
LVS in this case. But if you want to make it anyway, you can run CIW-

File->Export->CDL.

3. If you are using calibre as an LVS tool, then there is a utlity
called v2lvs. The V2LVS (Verilog-to-LVS) converter translates a
Verilog structural netlist into a LVS SPICE netlist suitable for
Calibre nmLVS/nmLVS-H comparison against a layout.

Hope this help.
Riad.

 

[S. Badel]

Pieter,

There are several ways to go about this. Depending on the data you have, and your LVS tool (in this
regard, as Riad pointed, I believe they have all more or less the same capabilities and requirements).

Essentially, you need a layout and a schematic...

For the layout, you can typically obtain a complete transistor-level layout in GDS format directly
from your P&R tool, provided you have the full layouts of your standard cells available. If it is
not the case, then you'll have to go for a gate-level LVS.

For the schematic... well the P&R tool does not bother with what's inside the cells, so typically
you can create a gate-level netlist only (in verilog format - cdl, maybe but I personally do not
like it).

The missing piece here is what's inside the cells (unless you go for gate-level...). It can be
available in different forms, from your library vendor. It could be SPICE or CDL netlists. It could
be a CDB/OA library with complete schematics. It could be a textual schematic such as EDIF.

Now you have to put all this together, and there are several ways to go about it as well. If you had
schematics for your cells, you may decide to import your verilog netlist into a gate-level
schematic, this way you'd have all the information in schematic form. You could also import the
verilog down to gate level, and include your standard cells netlists in the LVS run to complete the
information. Or, you could import nothing - just a symbol of your digital block that you'd place in
a schematic ; then you'd need to include your block's gate-level netlist in addition to the cells
transistor-level netlist into the LVS run.

That last option seems to be your choice. It would be mine too, as I said, I like to avoid all the
manipulations (such as importing the block) which take time at each turnaround, and may be error
factors.


Now after all this blabbering, I have merely restated your question How do you do it ? Simple :
import your verilog netlist into virtuoso with File->Import->Verilog. If you want only a symbol,
just set "Import structural modules as functional". If you want a schematic, set "Import structural
modules as schematic" and add your cell library in the "Reference Library" field, this way it will
use the symbols from that library to build up your schematic. If you don't have symbols for your
cell library, just create them before by importing the behavioral verilog description of your cells
into a new library to generate the symbols and functional views...

The last part is to properly setup your LVS tool to include the missing information (verilog netlist
of your digital block + transistor-level netlists of the cells). Here it depends on the particular
tool ; with assura you'd just add the file in "Netlisting Options". With calibre, as Riad mentioned,
you'd convert your verilog to a calibre-compliant CDL by using the command-line tool "v2lvs2" and
include all files in the run.


Feew. Hope it helps now... Cheers.
Stéphane

 

[pdw]

Hi Stephane and Riad,

thanks again for your responses! I'll try it out and let you know in
case I don't get it working!
Pieter


On Aug 25, 12:23 pm, "S. Badel" <stephane.ba...@REMOVETHISepfl.ch>
wrote:

Pieter,

There are several ways to go about this. Depending on the data you have, and your LVS tool (in this
regard, as Riad pointed, I believe they have all more or less the same capabilities and requirements).

Essentially, you need a layout and a schematic...

For the layout, you can typically obtain a complete transistor-level layout in GDS format directly
from your P&R tool, provided you have the full layouts of your standard cells available. If it is
not the case, then you'll have to go for a gate-level LVS.

For the schematic... well the P&R tool does not bother with what's inside the cells, so typically
you can create a gate-level netlist only (in verilog format - cdl, maybe but I personally do not
like it).

The missing piece here is what's inside the cells (unless you go for gate-level...). It can be
available in different forms, from your library vendor. It could be SPICE or CDL netlists. It could
be a CDB/OA library with complete schematics. It could be a textual schematic such as EDIF.

Now you have to put all this together, and there are several ways to go about it as well. If you had
schematics for your cells, you may decide to import your verilog netlist into a gate-level
schematic, this way you'd have all the information in schematic form. You could also import the
verilog down to gate level, and include your standard cells netlists in the LVS run to complete the
information. Or, you could import nothing - just a symbol of your digital block that you'd place in
a schematic ; then you'd need to include your block's gate-level netlist in addition to the cells
transistor-level netlist into the LVS run.

That last option seems to be your choice. It would be mine too, as I said, I like to avoid all the
manipulations (such as importing the block) which take time at each turnaround, and may be error
factors.

Now after all this blabbering, I have merely restated your question How do you do it ? Simple :
import your verilog netlist into virtuoso with File->Import->Verilog. If you want only a symbol,
just set "Import structural modules as functional". If you want a schematic, set "Import structural
modules as schematic" and add your cell library in the "Reference Library" field, this way it will
use the symbols from that library to build up your schematic. If you don't have symbols for your
cell library, just create them before by importing the behavioral verilog description of your cells
into a new library to generate the symbols and functional views...

The last part is to properly setup your LVS tool to include the missing information (verilog netlist
of your digital block + transistor-level netlists of the cells). Here it depends on the particular
tool ; with assura you'd just add the file in "Netlisting Options". With calibre, as Riad mentioned,
you'd convert your verilog to a calibre-compliant CDL by using the command-line tool "v2lvs2" and
include all files in the run.

Feew. Hope it helps now... Cheers.
Stéphane