D
Doaa Mahmoud
Guest
Hello people
Did any one before make a circuit using a transistor that identified by a verilog-A model and make LVS for this circuit,
because I have a problem when make extraction from schematic?
I think I should transform the verilog-A model to a netlist like in any transistor in analog lib. can any one know HOW ???
Did any one before make a circuit using a transistor that identified by a verilog-A model and make LVS for this circuit,
because I have a problem when make extraction from schematic?
I think I should transform the verilog-A model to a netlist like in any transistor in analog lib. can any one know HOW ???