LVS between DFII schematic and layout using Assura

[Min Pan]

Hello all. I have run into a problem with Assura.

Now I'm trying to do the LVS between the dfII schematic and layout.
When I run the Assura LVS, it always fail. I have checked the log
file. It seems that when Assura running the Nvn PreExtraction, it
tried to using dfIItoVldb to translate the schematic to vldb netlist
and caused some error. It gave the error message like the following.
--------------------------------------------------------------------
Library Name: "ami500mxsc5"
Cell Name: "inv1"
Cell View: "schematic"
Output Data Base Name: "/home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb"
Simulator Name: "auLvs"
View List: "auLvs schematic symbol"
Stop List: "auLvs"
Net Listing Mode is Analog
writing /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
inputting /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
Error - There can only be one vldb netlist in one network.
------------------------------------------------------------------------

I can't figure out why it always said "There can only be one vldb
netlist in one network." The Assura version is 3.0.

Any help is appreciated.

Thanks.

Min Pan
e-mail: panmin@iastate.edu

 

[Jay Lessert]

panmin@iastate.edu (Min Pan) wrote in message news:<f1332796.0307090612.7679e6c6@posting.google.com>...

writing /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
inputting /home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb
Error - There can only be one vldb netlist in one network.
------------------------------------------------------------------------

I can't figure out why it always said "There can only be one vldb
netlist in one network." The Assura version is 3.0.

I think because you've got something interesting going on, either
in the avCompareRules( schematic() ) section of your .rsf, and/or
in your .vlr.

I know this happens if you try to mix dfII and Verilog directly
from the GUI. Though it doesn't sound like you would be doing
this, for a single inverter.

So show us the little "extra" avCompareRules()
block down at the bottom of your .rsf, and the full content
(should be small) of the associated .vlr.

-Jay-

 

[Jay Lessert]

panmin@iastate.edu (Min Pan) wrote in message news:<f1332796.0307100703.3a2cecef@posting.google.com>...

Is there any possibility that the rule files(e.g. compare.rul,
bind.rul, extract.rul) can cause this problem. I've made some change
in those files. I think those files should not affect the conversion
from dfII to vldb netlist.

The extract.rul and binding file cannot affect it.

The compare.rul file technically could, if you put a
schematic(netlist()) section in it, right? Could happen
if one was careless with cut'n'paste.

avCompareRules(
schematic(
netlist( dfII "/home/panmin/ami500mxsc5/lvs/inv1/inv1.vlr" )
)
bindingFile("/remote/cadencelib/nda/ami06/kit/5.4/assura/bind.rul")
)

avSimName = "auLvs"
avLibName = "ami500mxsc5"
avCellName = "inv1"
avViewName = "schematic"
avViewList = "auLvs schematic symbol"
avStopList = "auLvs"
avVldbFile = "/home/panmin/ami500mxsc5/lvs/inv1/inv1.sdb"

These are fine.

-Jay-