LVS and verification

[weidong]

Hi, all:

Building up a chip with both custom block and standard cell in SE, some
questions about the LVS and verification of the circuit.

1. What is the tool to make LVS? Traditional LVS could not be applied
since we haven't detail layout info on the standard cells.

2. Verification of the chip. What is the proper tool(s) to verify the
timing and functionality of the circuit? Is LDV is good option?

Any suggestions are welcome. Thanks in advance!

/Weidong

 

[Diva Physical Verificatio]

You can use Diva macrocell extraction to get the standard cells as
primitive elements in the extracted view. The LVS can compare the
netlists at the standard cell level. This assumes the standard cells
have been properly built with the ivCellType property set to macro, and
NLP expression properties needed by the OSS netlister. I would be
surprised if the library vendor had not done this already.

On Fri, 02 Apr 2004 16:42:11 +0200, "weidongl<no_spam>"
<"weidongl<no_spam>"@isy.liu.se> wrote:

Hi, all:

Building up a chip with both custom block and standard cell in SE, some
questions about the LVS and verification of the circuit.

1. What is the tool to make LVS? Traditional LVS could not be applied
since we haven't detail layout info on the standard cells.

2. Verification of the chip. What is the proper tool(s) to verify the
timing and functionality of the circuit? Is LDV is good option?

Any suggestions are welcome. Thanks in advance!

/Weidong

 

[S. Badel]

I know Assura also has capability to do macro-cell lvs. They call
it blackBox however in the documentation. If you already have assura
rules it'll probably be easier, provided your abstract cells contains
df2 pins (that should probably be the case).
have a look at assura doc if interested.

stéphane

"weidongl<no_spam> @isy.liu.se>" <"weidongl<no_spam> wrote in message
news:c4ju43$j3i$1@news.island.liu.se...

Hi, all:

Building up a chip with both custom block and standard cell in SE, some
questions about the LVS and verification of the circuit.

1. What is the tool to make LVS? Traditional LVS could not be applied
since we haven't detail layout info on the standard cells.

2. Verification of the chip. What is the proper tool(s) to verify the
timing and functionality of the circuit? Is LDV is good option?

Any suggestions are welcome. Thanks in advance!

/Weidong