LVS and terminal mapping

[jools]

Hi

My design is failing LVS due to the terminal mapping. In the schematic
buses are of the format 'signal_1<7:0>' therefore a individual
terminal is 'signal_1<0>'. In the layout, after importing the DEF from
SE the terminals have been renamed as 'signal_1(0)' not 'signals_1<0>'
therefore the terminals don't match up. Even though in the DEF they
are of the format 'signal_1[0]' etc.

So the obvious thing to would be to use a correspondance file, which I
create by pointing at the corresponding pins in the schematic and
layout. But then the LVS fails due to an incorrect syntax error. The
correspondance file it creates is:

( #/signals_1(0) ) ( #/signals_1<0> )
etc.

And error from the LVS log is:

*WARNING* : Illegal name syntax - signals_1(0
si: Cannot map Cadence net name "/signals_1(0"( Cannot find net
signals_1(0 in cellview aes fsm_0dr extracted ).
si: simin did not complete successfully.
Unterminated macro name: '#/signals_1<0> )


Here is some of the terminal statements from the schematic netlist and
layout netlist:
schematic:
t 244 clk input
t 341 signals_0<7> output
t 106 signals_0<6> output
t 311 signals_0<5> output

layout:
t 369 clk input
t 52 signals_1\(7\) output
t 230 signals_1\(6\) output
t 11 signals_1\(5\) output

Any suggestions?

Thanks in advance

Jools

 

[Diva Physical Verificatio]

This error message is being generated during the netlist generation
phase. The OSS netlister has mechanisms for mapping a net name into LVS
net numbers. The problem is in your net name having a closing
parenthesis as a character. The correspondence file format requires net
names to be contained within an opening and closing parenthesis pair.

The name parser does not support an embedded closing parenthesis, so it
thinks the net name is "#/signals_1(0", which does not exist in the view
being netlisted. Nor does the parser support the use of a backslash to
"quote" the closing parenthesis.

A rigid interpretation of the documentation regarding the format of a
correspondence file would indicate that the closing parenthesis required
by the format should only be recognized when preceded by one or more
spaces. The Diva R&D team will accept a bug report to this effect. Not
that this will help you with your immediate problem.

The best, and most obvious, solution to your problem is to open the
layout you generated from DEF and modify the pin names to match the
names used in the schematic. Then regenerate the extracted view. Run LVS
without a correspondence file since the terminal names will be
sufficient. It is generally better to use the tool the way it is
intended than it is to attempt to finesse it.

On 30 May 2004 09:32:31 -0700, j.p.murphy@ncl.ac.uk (jools) wrote:

My design is failing LVS due to the terminal mapping. In the schematic
buses are of the format 'signal_1<7:0>' therefore a individual
terminal is 'signal_1<0>'. In the layout, after importing the DEF from
SE the terminals have been renamed as 'signal_1(0)' not 'signals_1<0>'
therefore the terminals don't match up. Even though in the DEF they
are of the format 'signal_1[0]' etc.

So the obvious thing to would be to use a correspondance file, which I
create by pointing at the corresponding pins in the schematic and
layout. But then the LVS fails due to an incorrect syntax error. The
correspondance file it creates is:

( #/signals_1(0) ) ( #/signals_1<0> )
etc.

And error from the LVS log is:

*WARNING* : Illegal name syntax - signals_1(0
si: Cannot map Cadence net name "/signals_1(0"( Cannot find net
signals_1(0 in cellview aes fsm_0dr extracted ).
si: simin did not complete successfully.
Unterminated macro name: '#/signals_1<0> )


Here is some of the terminal statements from the schematic netlist and
layout netlist:
schematic:
t 244 clk input
t 341 signals_0<7> output
t 106 signals_0<6> output
t 311 signals_0<5> output

layout:
t 369 clk input
t 52 signals_1\(7\) output
t 230 signals_1\(6\) output
t 11 signals_1\(5\) output

Any suggestions?

Thanks in advance

Jools

 

[S. Badel]

jools wrote:

hi,

her is a skill functions to allow mapping the names of all terminals
automatically. this function in fact allow mapping of a given
property on all of a given object of a cellview ( terminals, shapes,
instances, ... ) with regular expressions, so it is quite powerful.

example use :

rexList = list(
list( "(" "<" ) ; replace ( by <
list( ")" ">" ) ; replace ) by >
)
mapObjectsProp( "MYLIB" "MYCELL" "layout" 'terminals 'name rexList )

hope this helps,
stéphane







procedure( mapObjectsProp( lib cell view object property rexList )

prog( ( cv obj regexp objlist )

errset( cv = dbOpenCellViewByType( ddGetObj(lib) cell view nil "a" ) t )
; open cellview
when( !cv
error("Couldn't open cellview.\n")
) ; when

; check existence of objects and property
when( !dbGet( cv object )
error( sprintf( nil "Cannot find %s objects.\n"
symbolToString(object) ) )
)

; check existence of objects and property
when( !stringp(dbGet( car(dbGet( cv object )) property ))
error( sprintf( nil "%s objects do not have the %s property, or
property is not a string.\n" symbolToString(object)
symbolToString(property) ) )
)

; create list of object properties for mapping
objList = nil
foreach( obj dbGet(cv object)
objList = append( objList list( list( dbGet(obj property) dbGet(obj
property) ) ) )
) ; foreach

; apply list of regexps to list of properties
foreach( regexp rexList
rexCompile( car( regexp ) )
; walk through objects list
foreach( obj objList
rplacd( obj list( rexReplace( cadr(obj) cadr( regexp ) caddr( regexp
) ) ) )
) ; foreach

) ; foreach

; print header
printf( "Summary of %s %s mapping :\n" symbolToString( object )
symbolToString( property ) )

; apply new objects properties
foreach( obj dbGet(cv object)

; print summary
printf("%s -> %s\n" car( assoc( dbGet(obj property) objList ) ) cadr(
assoc( dbGet(obj property) objList ) ) )

dbSet( obj cadr( assoc( dbGet(obj property) objList ) ) property )

) ; foreach

dbSave( cv )
dbClose( cv )

return(t)
) ; prog

) ; procedure

Hi

My design is failing LVS due to the terminal mapping. In the schematic
buses are of the format 'signal_1<7:0>' therefore a individual
terminal is 'signal_1<0>'. In the layout, after importing the DEF from
SE the terminals have been renamed as 'signal_1(0)' not 'signals_1<0>'
therefore the terminals don't match up. Even though in the DEF they
are of the format 'signal_1[0]' etc.

So the obvious thing to would be to use a correspondance file, which I
create by pointing at the corresponding pins in the schematic and
layout. But then the LVS fails due to an incorrect syntax error. The
correspondance file it creates is:

( #/signals_1(0) ) ( #/signals_1<0> )
etc.

And error from the LVS log is:

*WARNING* : Illegal name syntax - signals_1(0
si: Cannot map Cadence net name "/signals_1(0"( Cannot find net
signals_1(0 in cellview aes fsm_0dr extracted ).
si: simin did not complete successfully.
Unterminated macro name: '#/signals_1<0> )


Here is some of the terminal statements from the schematic netlist and
layout netlist:
schematic:
t 244 clk input
t 341 signals_0<7> output
t 106 signals_0<6> output
t 311 signals_0<5> output

layout:
t 369 clk input
t 52 signals_1\(7\) output
t 230 signals_1\(6\) output
t 11 signals_1\(5\) output

Any suggestions?

Thanks in advance

Jools