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ejm20Rick
Guest
Im looking for a way to instantiate a metal cap in the schematic and layout and have assura check for the connectivity. The value will be hardcoded. I have created an almost working solution using the auLvs view and CDF's and it does netlist correctly but Assura is flattening it so it produces pin errors and the top level is not checked. Ive seen this problem when blackboxing and you need to use the promote child option.
Maybe this is the wrong approach since I only really need this structure to be checked for connectivity but it would be nice to have it also netlist as a capacitor. Once this part is done, then it will be extracted and the real value will be hardcoded into the device....currently as the defValue in the CDF's
Rick
Maybe this is the wrong approach since I only really need this structure to be checked for connectivity but it would be nice to have it also netlist as a capacitor. Once this part is done, then it will be extracted and the real value will be hardcoded into the device....currently as the defValue in the CDF's
Rick