LVDS simulation in Hyperlynx

[maxascent]

I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA.
would like to use the DCI termination but when I select this model th
simulation complains that it cant perform it because it cant model a serie
resistor at the receiver input. I assume this is something to do with th
termination but I am not sure what I am supposed to do.

Thanks

Jon

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[Brian Davis]

maxascent wrote:

I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA.
snip
when I select this model the simulation complains that it cant perform
it because it cant model a series resistor at the receiver input.

What version of Hyperlynx are you using?

When I checked a few years back, 7.5 & earlier couldn't handle the
series elements:
http://groups.google.com/group/comp.arch.fpga/msg/c6e28cb7cc0ce3d0

Brian