LVDS in cyclone

[Eduard Nikke]

Hi,

Can someone help me with this issue.

I am looking to build a serialer in a FPGA.
Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of
504MBps.

I thought this wat not possible in a Cyclone device but just reads the app.
note and it seems to be possible.

I have only some strong concerns because there is no timing budget and the
IOB are not DDR IOB blocks.

Does any one has experience with this app. note ?

Thanks,

Eduard

 

[Vaughn Betz]

"Eduard Nikke" <ednikke@hotmail.com> wrote in message news:<SEJ7b.12842$MJ3.93276@phobos.telenet-ops.be>...

Hi,

Can someone help me with this issue.

I am looking to build a serialer in a FPGA.
Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of
504MBps.

I thought this wat not possible in a Cyclone device but just reads the app.
note and it seems to be possible.

I have only some strong concerns because there is no timing budget and the
IOB are not DDR IOB blocks.

Does any one has experience with this app. note ?

Thanks,

Eduard

Hi Eduard,

I believe you are referring to app note:
http://www.altera.com/literature/hb/cyc/cyc_c51009.pdf

What it says is correct -- Cyclone can do 640 Mb/s LVDS. More
specifically, the -6 and -7 speed grades are characterized
(guaranteed) to do 640 Mb/s LVDS, while the -8 (slowest) is only
currently characterized for up to 550 Mb/s LVDS.

Regards,

Vaughn
Altera