LUT, how to?

[Giox]

Hello everybody, I'm a newbye in FPGA so I need some help in a simple
problem.
I would like to implement a 256 byte LUT on a Virtex 300 E FPGA.
Can you suggest me some on line resource that explains how to implement
this LUT, how to select the memory resources that I want use for this
task etc?
Thanks a lot for any help, Giovanni

 

[Neo]

the tool will automatically infer distributed ram if you can do without
a reset.

 

[Giox]

can you provide me some reference to the documentation that documents
that?
Moreover a LUT of 256 byte has an acceptable size or is too big?
I know this is a stupid question, but I'm a newbye
Thanks a lot

 

[Giox]

In fact you are right, this is what I was searching for, but I didn't
know what was the better way to implement it.
Now with your help I found it. Thanks Gio

 

[Peter Sommerfeld]

Hi,

There's a few ways to do this. For Xilinx you would probably want to go
through Coregen and implement a ROM with an init file.

You can also built the LUT entirely out of slices (as opposed to the
specialize block memory structures) by using generic code. Below is an
example that should work for probably any FPGA (Xilinx, Altera, etc).
The LUT contents are define in-line, so it's not as nice as using a
data file. (I'm lazy, so it's only an 8-entry 8-bit LUT).

Finally, for simulation only, you can use the Verilog block "initial"
to and $readmemb to read from a file. This won't work if you want to
synthesize to real hardware like the code below.

-- Pete

module lut
#(
parameter INPUT_WIDTH = 3,
parameter DATA_WIDTH = 8
)
(
input clk, reset,
input [INPUT_WIDTH-1:0] in,
output reg [DATA_WIDTH-1:0] out
);

wire [DATA_WIDTH-1:0] my_lut_values[2**INPUT_WIDTH-1:0];
wire [0ATA_WIDTH*(2**INPUT_WIDTH)-1] my_lut_string;

// my string of values that will initialize the LUT: A0, B7, 15, C3,
11, 22, 33, 44
assign my_lut_string = { 64'ha0b715c318223344 };

// put the initialization string into the LUT array
genvar i;
generate
for (i=0; i < 2**INPUT_WIDTH; i=i+1)
begin: part_select
assign my_lut_values = my_lut_string[(i+1)*DATA_WIDTH-1 -:
DATA_WIDTH];
end
endgenerate

// do the lookup
always @(posedge clk)
begin
if (reset)
out <= 8'b0;
else
out <= my_lut_values[in];
end

endmodule

 

[Giox]

Thanks a lot to everybody for your help, now my task is much more
evident
Giovanni

 

[Peter Alfke]

Giovanni,
I am a big fan of using BlockRAMs for "unusual" applications.
But here is one warning:
All Xilinx BlockRAM are synchronous devices, which means, changing the
address input has no effect on the output, until you apply the right
clock edge.
While conventional static ROMs may not require a clock, the Virtex and
Spartan BlockROMs do ( and I think the competition uses a similar
structure).
In most cases the clocked operation is no problem, in some cases it is
a big advantage, and sometimes it is a pain...
Peter Alfke, Xilinx Application