LUT and latch in the FPGA

[ric]

Hi,guys!
I have maybe a silly question,but it confused me all the day,the
question is:
I have a function with 5-inputs and one output,and thus XST maps to
2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
about 5000 such functions in my design.So I want to use a 4-input LUT
and a D-LATCH with async clear instead(one of the 5-inputs is used to
clear the output).But,the question is,I do use the LUT and latch in
the same slice,but the other LUT in the same slice can not be used by
other logic!
Why my method could not work?Is there any resource conflict?
Appreciate for your help!Thanks!

ps.
My verilog code is like this:
always @ (zero_flag or a or b )
if (zero_flag)
o_tmp_data <= 14'h0 ;
else if (b[1:0] == 2'b00)
o_tmp_data <= a[13:0] ;
else if (b[1:0] == 2'b01)
o_tmp_data <= {a[12:0],1'b0} ;
else if (b[1:0] == 2'b11)
o_tmp_data <= ~a[13:0] ;
else
o_tmp_data <= {~a[12:0],1'b1} ;
or I use two blocks and the other block is exactly like what Xilinx
suggests in its template,but the XST could not recognize it as a LUT
and a latch,and still 2 LUTs.I wonder if I miss something?

 

[rickman]

ric wrote:

Hi,guys!
I have maybe a silly question,but it confused me all the day,the
question is:
I have a function with 5-inputs and one output,and thus XST maps to
2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
about 5000 such functions in my design.So I want to use a 4-input LUT
and a D-LATCH with async clear instead(one of the 5-inputs is used to
clear the output).But,the question is,I do use the LUT and latch in
the same slice,but the other LUT in the same slice can not be used by
other logic!
Why my method could not work?Is there any resource conflict?
Appreciate for your help!Thanks!

ps.
My verilog code is like this:
always @ (zero_flag or a or b )
if (zero_flag)
o_tmp_data <= 14'h0 ;
else if (b[1:0] == 2'b00)
o_tmp_data <= a[13:0] ;
else if (b[1:0] == 2'b01)
o_tmp_data <= {a[12:0],1'b0} ;
else if (b[1:0] == 2'b11)
o_tmp_data <= ~a[13:0] ;
else
o_tmp_data <= {~a[12:0],1'b1} ;
or I use two blocks and the other block is exactly like what Xilinx
suggests in its template,but the XST could not recognize it as a LUT
and a latch,and still 2 LUTs.I wonder if I miss something?

You didn't say which Xilinx part you are using and I am not intimate
with all of them. But generally you can't use two different signals for
the async control of the FFs in a slice. The async control is shared
between the two FFs.

Perahps you can find common signals to your 5 input functions and
combine them in a LUT. This signal can be run to a group of 4 input
functions which will then each fit in a single LUT.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Martin Euredjian]

Use FPGA Editor to look at the diagram of a single slice. You'll see what
logic and interconnection possibilities you have within the confines of a
slice. In fact, you can even switch to editing mode and make connections
manually. See if you can figure out how to pack your logic in there this
way.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"





"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0310170151.da838dd@posting.google.com...

Hi,guys!
I have maybe a silly question,but it confused me all the day,the
question is:
I have a function with 5-inputs and one output,and thus XST maps to
2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
about 5000 such functions in my design.So I want to use a 4-input LUT
and a D-LATCH with async clear instead(one of the 5-inputs is used to
clear the output).But,the question is,I do use the LUT and latch in
the same slice,but the other LUT in the same slice can not be used by
other logic!
Why my method could not work?Is there any resource conflict?
Appreciate for your help!Thanks!

ps.
My verilog code is like this:
always @ (zero_flag or a or b )
if (zero_flag)
o_tmp_data <= 14'h0 ;
else if (b[1:0] == 2'b00)
o_tmp_data <= a[13:0] ;
else if (b[1:0] == 2'b01)
o_tmp_data <= {a[12:0],1'b0} ;
else if (b[1:0] == 2'b11)
o_tmp_data <= ~a[13:0] ;
else
o_tmp_data <= {~a[12:0],1'b1} ;
or I use two blocks and the other block is exactly like what Xilinx
suggests in its template,but the XST could not recognize it as a LUT
and a latch,and still 2 LUTs.I wonder if I miss something?

 

[ric]

Sorry for my carelessness--the device is xc2vp40-6-1152,and the two
LUTs share the same reset signal.
Let me introduce my design clearly:
The function is a multiplier of 15*3,both multiplicators are 2's
complement,
say a[14:0] and b[2:0];b can be 0,+1,+2,-1 or -2(for
ethernet,4D/PAM5).So the function is actually a mux,the output o[n]
needs 5 inputs:a[n],a[n-1] and
b[2:0].So I think use a 4-input(a[n],a[n-1],b[1:0]--change encoding)
LUT and a D-latch(reset active when b is 3'h0) may save area in FPGA
design.Are there some other good methods?
In fact I do use FPGA Editor to generate a macro(since "clever"
method did not work),but it brings out other questions -_-!
First I generate a macro with only one LUT,but placer failed with a
warning like "can not place function",I think maybe ISE considers the
macro as a whole slice which contains only one LUT,so the design is
too large to put in the device(remember there is 5k such functions
here).But why the warning message appears at place stage and not map
stage?And I think this problem is something like the RPM,right?But I
could not find the reason why it is like this and how to avoid.
Secondly I generate another macro fully using the whole slice(but my
design uses only 3 of the 4--an eclectic solution).This time the
warnings dissapear but it takes a very long time and routing process
seems never convergent,so I stop it.
Do you have any suggestion?Thanks a lot!

Best Regards,
Ric Ma
ASIC Department
@Attansic Inc.

 

[ric]

A new progress:
I re-implement the design without LOC constraints(in translate
stage) using my one-slice macro,after 12 hours of routing,the par
failed and there's always
1556 unrouted,and the ISE "keeps" the relative position of the slice
in the CLB.It seems to be the reason for the routing error,but how can
I resolve it?Is there some hidden option when I create the macro?
And sorry for my mistake in the last post:
........

First I generate a macro with only one LUT,but placer failed with a
~~~~~~~

one slice
.......

Secondly I generate another macro fully using the whole slice(but my
~~~~~~

CLB

Have a nice day!

 

[ric]

Here comes the end..
The problem IS brought by the macro's reference comp(or something
like that , I am not sure),because the placed macros(one slice each)
are at the same position in the CLBs,and this reduces much routing
agility . But in the design of the macro , I can not modify the
attribute to let it not remember the position in the CLB . What I do
is after the "map" process of the whole design , read in the ncd file
in FPGA Editor and select all the macros and unbind them,then the tool
will take all of them as ordinary components,and the PAR would not
fail.Also , the area is saved by the use of these macros . In my
design , the slice usage drops from 89% to 78%(XC2VP40).
That's all,hope it helps , though seems just like talking to
myself...Well,
glad to be here and thank you for all the help , have a nice day!