LTSpice newbie: simple model won't analyze

W

Walter Harley

Guest
I'm hoping someone here can educate me on how to work through a simple
problem in LTSpice. (I'll also try the Yahoo group, but I'm having troubles
with that web page just now.)

I have a simple circuit with two NOR gates, a resistor, and a capacitor.
(Some of you might recognize it from a recent s.e.d posting.) I've appended
the LTSpice .asc contents below. When I try simulating it, I get this
error:
"Analysis: Timestep too small; initial timepoint: trouble with
or-instance a1".

None of the obvious options on the simulation command seem to make any
difference. One possibility is that I'm not using the OR gate correctly; per
the online help, I'm leaving unused inputs unconnected. But I also tried
grounding the unused inputs, and that didn't seem to make much difference.

So, what do I need to do to get this to simulate successfully?


LTSpice model follows:
Click to expand...
Version 4
SHEET 1 880 680
WIRE 64 208 96 208
WIRE 160 208 208 208
WIRE 208 160 208 208
WIRE 208 208 256 208
WIRE 320 256 352 256
WIRE 352 256 352 176
WIRE 352 48 208 48
WIRE 208 48 208 80
WIRE 208 48 -32 48
WIRE -32 48 -32 160
WIRE -32 160 0 160
WIRE 352 176 352 48
WIRE 16 224 16 256
WIRE 272 272 272 304
FLAG 352 176 Vo
FLAG 16 256 0
FLAG 272 304 0
SYMBOL Digital\\or 32 128 R0
SYMATTR InstName A1
SYMBOL Digital\\or 288 176 R0
SYMATTR InstName A2
SYMBOL cap 160 192 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 1ľF
SYMBOL res 192 64 R0
SYMATTR InstName R1
SYMATTR Value 1k
TEXT 64 288 Left 0 !.tran 10ms
 
"Mike Engelhardt" <pmte@concentric.net> wrote in message
news:c6bmdn$on@dispatch.concentric.net...
The problem is that those gates have no delay by default.
Hence, the circuit sees a race condition. Right click on
on of the Gate, and add a value of "Td=10n" to give the
gate a 10ns delay. Then your circuit has a solution.
Click to expand...
That works great! (Actually, with Td=10n on one gate, it took a long time
to simulate; with Td=10n on one and Td=15n on the other, it was
instantaneous.)

Thanks for the quick answer.
 
"Walter Harley" <walterh@cafewalterNOSPAM.com> schrieb im Newsbeitrag
news:c6bn5k$jhl$0@216.39.172.65...
"Mike Engelhardt" <pmte@concentric.net> wrote in message
news:c6bmdn$on@dispatch.concentric.net...
The problem is that those gates have no delay by default.
Hence, the circuit sees a race condition. Right click on
on of the Gate, and add a value of "Td=10n" to give the
gate a 10ns delay. Then your circuit has a solution.

That works great! (Actually, with Td=10n on one gate, it took a long time
to simulate; with Td=10n on one and Td=15n on the other, it was
instantaneous.)
Click to expand...
Hello Walter,
thanks for this tipp with the different delay time td.
I wouldn't believe it, if I hadn't tried it.

The simulation of this circuit either stucks at a fixed level
or breaks into a wrong high frequency oscillation when using
an equal delay time(10n) for both OR-gates.
The behavior depends on the choosen solver. It seems to be a
problem of symmetry.

I will mention this tipp in the LSPICE Yahoo group if I post
something about digital parts in the future.

Best Regards,
Helmut
 
The problem is that those gates have no delay by default.
Hence, the circuit sees a race condition. Right click on
on of the Gate, and add a value of "Td=10n" to give the
gate a 10ns delay. Then your circuit has a solution.

--Mike


"Walter Harley" <walterh@cafewalterNOSPAM.com> wrote in message news:c6bm0t$ar5$0@216.39.172.65...
I'm hoping someone here can educate me on how to work through a simple
problem in LTSpice. (I'll also try the Yahoo group, but I'm having troubles
with that web page just now.)

I have a simple circuit with two NOR gates, a resistor, and a capacitor.
(Some of you might recognize it from a recent s.e.d posting.) I've appended
the LTSpice .asc contents below. When I try simulating it, I get this
error:
"Analysis: Timestep too small; initial timepoint: trouble with
or-instance a1".

None of the obvious options on the simulation command seem to make any
difference. One possibility is that I'm not using the OR gate correctly; per
the online help, I'm leaving unused inputs unconnected. But I also tried
grounding the unused inputs, and that didn't seem to make much difference.

So, what do I need to do to get this to simulate successfully?


LTSpice model follows:

Version 4
SHEET 1 880 680
WIRE 64 208 96 208
WIRE 160 208 208 208
WIRE 208 160 208 208
WIRE 208 208 256 208
WIRE 320 256 352 256
WIRE 352 256 352 176
WIRE 352 48 208 48
WIRE 208 48 208 80
WIRE 208 48 -32 48
WIRE -32 48 -32 160
WIRE -32 160 0 160
WIRE 352 176 352 48
WIRE 16 224 16 256
WIRE 272 272 272 304
FLAG 352 176 Vo
FLAG 16 256 0
FLAG 272 304 0
SYMBOL Digital\\or 32 128 R0
SYMATTR InstName A1
SYMBOL Digital\\or 288 176 R0
SYMATTR InstName A2
SYMBOL cap 160 192 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 1ľF
SYMBOL res 192 64 R0
SYMATTR InstName R1
SYMATTR Value 1k
TEXT 64 288 Left 0 !.tran 10ms
Click to expand...
 
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