LRM: Double-block instantiations

[valtih1978]

Specification says "A component instantiation is equivalent to a pair of
nested block statements that couple the block hierarchy in the
containing design unit to a unique copy of the block hierarchy contained
in another design unit (i.e., the subcomponent). The outer block
represents the component instantiation statement; the inner block
represents the design entity to which the instance is bound. Each is
defined by a block statement."

You do not understand what is the issue unless first time look at the
example

entity X is
port (P1, P2: inout BIT);
constant Delay: TIME := 1 ms;
begin
...
end entity X;

architecture Y of X is
begin
...
end architecture Y;

Spec then specifies that instantiation

C: entity Work.X (Y) port map (P1 => S1, P2 => S2);

is identical to

C: block -- Instance block.
begin
X: block -- Design entity block.
port (P1, P2: inout BIT); -- Entity interface ports.
port map (P1 => S1, P2 => S2);
constant Delay: TIME := 1 ms; -- Entity declarative item.
begin
...
end block X;
end block C;

I wonder, what is the purpose of doing that and why everybody, eg.
Modelsim, behave as there is only one block? For instant, I always used
to refer C.P1 instead of C.X.P1 in whatever tool I use as if there is
only one hierarchical block.