V
vadim
Guest
I am implementing a SERDES transceiver using the
LPM_SHIFTREG as serializer. In simulations, the
register loads new parallel word only when
the load signal is active during the time
when clock is '0'. The help states that it should
be active on the +ve clock edge.
I can't find any reasonable documentation about this
megafunction, so wonder if anyone know what might be the problem ?
(The target is Stratix device. The reason I am not using the Megafunction
SERDES transceiver is because it can be used only above 300Mbps)
Vadim
LPM_SHIFTREG as serializer. In simulations, the
register loads new parallel word only when
the load signal is active during the time
when clock is '0'. The help states that it should
be active on the +ve clock edge.
I can't find any reasonable documentation about this
megafunction, so wonder if anyone know what might be the problem ?
(The target is Stratix device. The reason I am not using the Megafunction
SERDES transceiver is because it can be used only above 300Mbps)
Vadim