Low Power RTL Design

Guest
Hi All..
I'm now about to carry a low-power design, I've searched the net for
low power design resources, but most of the resources on the web are
focused on low power design tactics at the back end.

On the other hand, I didn't find any resources about good RTL design
techniques for low power, except for the vague 6 pages in the RMM and
some other papers that are much concerned with the power estimation
rather than power reduction techniques.

Anyone has any information, links, or personnal expertise that can
share it with me.

Best regards,
Hosni
 
mhosni80@gmail.com wrote:
Hi All..
I'm now about to carry a low-power design, I've searched the net for
low power design resources, but most of the resources on the web are
focused on low power design tactics at the back end.

On the other hand, I didn't find any resources about good RTL design
techniques for low power, except for the vague 6 pages in the RMM and
some other papers that are much concerned with the power estimation
rather than power reduction techniques.

Anyone has any information, links, or personnal expertise that can
share it with me.

Best regards,
Hosni

I'm no expert in low power design, but many logic-design related
conferences should have papers on low-power design. Try conferences like
MAPLD or SNUG.
 

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