Loops for write access

[JSreeniv]

Hi all,
I am writing a VHDL Testbench for my simulation...and i got some
complexity to describe the writing data for 25 times.
Where my WRITE Access is
write
(x"02181",x"0000_0001",dsp_ardy,dsp_oe_n,dsp_re_n,dsp_we_n,dsp_ce_n,dsp_d,dsp_a,dsp_clk,por_n,test_fpga_oe,test_en);

Here x"02181" is hexadecimal and x"0000_0001" is data and i need to
write data with increment of address by 1 everytime and also data for
25 times.

Writing each time whole this process can be complex..so i am looking
for any simple idea...

Please suggest me..
Thanks

 

[Brian Drummond]

On Sun, 16 Aug 2009 21:16:59 -0700 (PDT), JSreeniv <sreenivas.jyothi@gmail.com>
wrote:

Hi all,
I am writing a VHDL Testbench for my simulation...and i got some
complexity to describe the writing data for 25 times.
Where my WRITE Access is
write
(x"02181",x"0000_0001",dsp_ardy,dsp_oe_n,dsp_re_n,dsp_we_n,dsp_ce_n,dsp_d,dsp_a,dsp_clk,por_n,test_fpga_oe,test_en);

Here x"02181" is hexadecimal and x"0000_0001" is data and i need to
write data with increment of address by 1 everytime and also data for
25 times.

Writing each time whole this process can be complex..so i am looking
for any simple idea...

Please suggest me..

Use a wrapper procedure to simplify it. Remember that overloaded procedures can
be resolved by their parameter lists, so you can still call it "write".

procedure write(Addr : std_logic_vector(31 downto 0);
Data : std_logic_vector(31 downto 0)) is
begin
write( Addr, Data, dsp_ardy, dsp_oe_n, dsp_re_n, dsp_we_n, dsp_ce_n, dsp_d,
dsp_a, dsp_clk, por_n, test_fpga_oe, test_en);
end;

write (x"02181",x"0000_0001);

- Brian

 

[JimLewis]

Hi Sreenivas,
You can also do this with records. It is a little more
difficult since you must initialize the record signal to
all 'Z', it leaves less stuff in the stimulus generation
portion of the testbench.

Best,
Jim

 

[JSreeniv]

On Aug 17, 9:07 pm, JimLewis <J...@SynthWorks.com> wrote:

Hi Sreenivas,
You can also do this with records.  It is a little more
difficult since you must initialize the record signal to
all 'Z', it leaves less stuff in the stimulus generation
portion of the testbench.

Best,
Jim

Hi Jim and Brain,
Where from my question i done using defined variables and a while loop
which is good to use in simulations.
from the WRITE access the address is X"02181" and Data:X"0000_0001"

Here is the piece of code:
stimulus: process
variable m1: std_logic_vector(19 downto 0) = X"02181";
variable n1: std_logic_vector(31 downto 0) = X"0000_0001";
---
---
I:=1;
while(I<=25) loop
WRITE(m1+1, n1+1,dsp_ardy, dsp_oe_n, dsp_re_n, dsp_we_n, dsp_ce_n,
dsp_d,
dsp_a, dsp_clk, por_n, test_fpga_oe, test_en);
I:I+1;
end loop;

where my data is increment of 1 or walkin-1's; So is this good way of
implement for Testbench simulation and efficiency..or please suggest
your inputs

Sreeni

 

[Andy]

On Aug 17, 11:19 am, JSreeniv <sreenivas.jyo...@gmail.com> wrote:

On Aug 17, 9:07 pm, JimLewis <J...@SynthWorks.com> wrote:

Hi Sreenivas,
You can also do this with records.  It is a little more
difficult since you must initialize the record signal to
all 'Z', it leaves less stuff in the stimulus generation
portion of the testbench.

Best,
Jim

Hi Jim and Brain,
Where from my question i done using defined variables and a while loop
which is good to use in simulations.
from the WRITE access the address is X"02181" and Data:X"0000_0001"

Here is the piece of code:
stimulus: process
variable m1: std_logic_vector(19 downto 0) = X"02181";
variable n1: std_logic_vector(31 downto 0) = X"0000_0001";
---
---
I:=1;
while(I<=25) loop
WRITE(m1+1, n1+1,dsp_ardy, dsp_oe_n, dsp_re_n, dsp_we_n, dsp_ce_n,
dsp_d,
           dsp_a, dsp_clk, por_n, test_fpga_oe, test_en);
I:I+1;
end loop;

where my data is increment of 1 or walkin-1's; So is this good way of
implement for Testbench simulation and efficiency..or please suggest
your inputs

Sreeni

You probably want to "WRITE(m1+I, n1+I,...".

If your while-loop is acting like a for-loop, then use a for-loop,
simulation or not:

for I in 1 to 25 loop
....

Andy