Looking for HDL code for sin( a ) and x ** y Functions

[Derek Simmons]

Before I get spamed for this I have done a search and I see there are
references to what I'm looking for on www.opencores.org but for some
reason I'm unable to connect.

What I'm looking for is a resource like, if it existed, Numerical
Receipes in HDL (VHDL/Verilog). I have a need for the basic floating
point functions like sin( a ) and x ** y. For floating point numbers
that are only 12 to 18 bits I can use lookup tables but I was wondering
if there was another way of calculating these values. Most of the books
I have cover addition/subtraction, multiplication and division but
nothing more advance or even hints at how to go about it.

From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a
), and yth root of x.

I'm looking for any helpful or constructive suggestions.

Thanks,
Derek

 

[Andrew FPGA]

What I'm looking for is a resource like, if it existed, Numerical
Receipes in HDL (VHDL/Verilog).

Elementary Functions, Algorithms and Implementation by Jean-Michel
Muller.
No HDL code but the algorithms are there.

 

Derek Simmons wrote:

From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a
), and yth root of x.

Integer exponents are pretty straightforward. It is a similar
algorithm to multiplication (multiply by 2 and optionally add), but
with higher order operations (square and optionally multiply).

Integer roots are probably best done by something like Newton-Raphson.

Arbitrary powers probably require computing logarithms first. One
issue with that is that you can't compute them for negative numbers.
If you just want integer roots, computing arbitrary powers probably
isn't the best way to do it.

 

[Ray Andraka]

Derek Simmons wrote:

Before I get spamed for this I have done a search and I see there are
references to what I'm looking for on www.opencores.org but for some
reason I'm unable to connect.

What I'm looking for is a resource like, if it existed, Numerical
Receipes in HDL (VHDL/Verilog). I have a need for the basic floating
point functions like sin( a ) and x ** y. For floating point numbers
that are only 12 to 18 bits I can use lookup tables but I was wondering
if there was another way of calculating these values. Most of the books
I have cover addition/subtraction, multiplication and division but
nothing more advance or even hints at how to go about it.

From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a
), and yth root of x.

I'm looking for any helpful or constructive suggestions.

Thanks,
Derek

It really depends on your precision and accuracy requirements. For
arbitrarily high precision, CORDIC is the way to go for sin provided you
can live with the latency. The other end of the spectrum is a look-up
table. There are intermediate solutions which are generally a
combination of angular reductions and interpolation that will get you a
reasonably high resolution without a huge look-up table. Linear
interpolation perhaps the easiest, and can be done with relatively
little hardware. A parabolic fit interpolation will get you
considerably smaller errors between table entries allowing a finer
resolution, and can be done with relatively low hardware complexity.

For X**Y, it is easiest to work with normalized floating point as an
input, and then using interpolated LUTs. Normalizing limits the range
of the tables. For a general purpose trancendental function calculator,
your best bet might be a CORDIC-like iterative engine, as CORDIC and
CORDIC-like structures can handle trig, hyperbolic trig, logs and
exponents, and multiply and divide.

So the point is, that there are many ways to skin this cat, and the
"best" way depends heavily upon your particular requirements.

 

[Ray Andraka]

Ray Andraka wrote:

By the way, I have a paper on CORDIC on my web site that many have found
ot be quite useful. Http://www.andraka.com/papers see: A survey of
CORDIC algorithms for FPGA based Computers.

I also second the reference to Jean Muller's book elementary functions
book for algorithms, although you may have difficulty translating it
into hardware.

 

Ray,

In case your company uses Synopsys tools, there is a very simple
solution available in their DesignWare library. They have both hardware
as well as simulation models for both the above functions, which can be
simply instantiated in the code. If you are not looking for any
specific algorithm that implements the functions (and if you have
access to the library) then this could be the right solution.

-Sourabh

Disclaimer: This is not push anyone's marketing agenda; just
information about a solution for the given problem.

 

[MariuszK]

Hello,

Try this:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

Mariusz

 

[Derek Simmons]

cbr_929rr wrote:

If www.opencores.org link does not work, try
http://www.opencores.org:8080/

The port number fixed my problems with connecting.

Thanks,
Derek

 

[Derek Simmons]

Andrew FPGA wrote:

What I'm looking for is a resource like, if it existed, Numerical
Receipes in HDL (VHDL/Verilog).

Elementary Functions, Algorithms and Implementation by Jean-Michel
Muller.
No HDL code but the algorithms are there.

I found a couple of people have recommended this book and when I did a
quick search on Amazon it came highly recommended. I'm looking into
getting a copy.

Thanks,
Derek

 

[Derek Simmons]

It really depends on your precision and accuracy requirements. For
arbitrarily high precision, CORDIC is the way to go for sin provided you
can live with the latency. The other end of the spectrum is a look-up
table. There are intermediate solutions which are generally a
combination of angular reductions and interpolation that will get you a
reasonably high resolution without a huge look-up table. Linear
interpolation perhaps the easiest, and can be done with relatively
little hardware. A parabolic fit interpolation will get you
considerably smaller errors between table entries allowing a finer
resolution, and can be done with relatively low hardware complexity.

I can live with the latency because the math unit I'm designing is
pipelined. As long as I organize the operations putting the ones with
longest latency first and at the cost of a multiplier or adder I should
keep a couple of parallel tracks busy.

For X**Y, it is easiest to work with normalized floating point as an
input, and then using interpolated LUTs. Normalizing limits the range
of the tables. For a general purpose trancendental function calculator,
your best bet might be a CORDIC-like iterative engine, as CORDIC and
CORDIC-like structures can handle trig, hyperbolic trig, logs and
exponents, and multiply and divide.

I'm comparing the trade off for using a lookup table to using an
iterative process. I have designed a general purpose rasterizer. I can
feed it a canned list of triangles in screen coordinates and it can
render them shaded. I'm working my way backwards up the pipeline to
design the geometry engine stage. Given the parameters for viewing
transformations I'm adding the functionality to build the viewing
transforms, using the object space coordinates calculate the world
space coordinates and from the worldspace coordinates calculate the
screen coordinates for the rasterizer.

Right now I'm doing this with the attitude of a hobby but I would like
to roll it over into something professional. Much of what I'm doing is
iterative, it never amazes me when QuartusII finds a flaw in one of my
state machines and decides to flatten it.

Thanks,
Derek

 

Derek Simmons wrote:

Andrew FPGA wrote:
What I'm looking for is a resource like, if it existed, Numerical
Receipes in HDL (VHDL/Verilog).

Elementary Functions, Algorithms and Implementation by Jean-Michel
Muller.
No HDL code but the algorithms are there.

I found a couple of people have recommended this book and when I did a
quick search on Amazon it came highly recommended. I'm looking into
getting a copy.

Thanks,
Derek

Another book to consider is -

DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN USING VERILOG HDL by James
Stine.

It has a 25 page chapter on Elementary Functions; the style of the book
is to sketch the algorithm and then show the verilog code for typically
a 16 bit implementation at the hierarchic gate level.