Log into solvnet (solvnet.synopsys.com) and download the user guide for
Formality.
But, normal designs are quite simple to handle:
1) read in the technology libraries
2) read in the reference designs
3) read in the implementation designs
4) match
4.bis) resolve unmatched compare points
5) verify
5.bis) look into failing points
Things get harder if you use a lot of optimized arithmetic with the old VHDL
parser in DC (or if you use a different synthesis tool).
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